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Silly nomenclature question: is there any reason at all why all the <architecture>-E chips are one number too high in the "thousands place"? Sandy Bridge CPUs were 2xxx, Sandy Bridge-E were 3xxx, Ivy Bridge were 3xxx, Ivy Bridge-E were 4xxx, and now Haswell CPUs are 4xxx and Haswell-E are 5xxx and Broadwell will probably be 5xxx and a hypothetical Broadwell-E will be 6xxx and so on. That seems like a pointless and confusing decision. Did Intel ever explain this?
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Sep 25, 2014 06:14
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It should have been Core 3.
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Apr 14, 2015 03:01
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Lord Windy posted:Is Hyper Threading decent? If you had two equally powered devices, would the one with hyper threader perform better in multithreading activities? Yes, but the performance improvement isn't as good as adding more physical cores. So if you need lots of threads running in parallel, eight cores > four cores with HT > just four cores.
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Apr 28, 2015 04:48
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SpelledBackwards posted:But you can only get 128 GB if you can prove you're sufficiently hardcore. This is amazing. "EIGHT OF A KIND"
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Jun 28, 2015 03:37
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HalloKitty posted:I didn't really read too much into it, but suddenly I'm whisked back a few years to the time of the announcement that memristors would be replacing our storage and RAM by.. 2013. ...Whatever happened to the memristor, anyway?
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Jul 31, 2015 05:08
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Rastor posted:
that's what the USB port said
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Aug 18, 2015 02:02
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quote:CORRECTION: Due to a reporting error, an earlier version of the story misidentified the product that has been retired. It is the Skylake-C and not the Broadwell-C that has been discontinued. Changes have been made throughout the story to reflect the change. I'm guessing there's a similar chip in the works for Kaby Lake. I can't imagine Intel completely throwing out the "let's have an enormous L4 cache" idea, surely there's some niche somewhere that'll pay Intel big money for those CPUs.
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Sep 18, 2015 02:06
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The real shortage was the friends we made along the way
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Dec 8, 2016 03:23
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Does anyone remember that article that showed that RAM frequency was important for frametime consistency on Intel CPUs from the last few years? I think it at least covered Sandy bridge through haswell, and basically demolished the old "ram frequency doesn't matter at all" mantra that was common for a long time. Was written about one or two years ago iirc
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May 13, 2017 00:38
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Jago posted:http://www.eurogamer.net/articles/digitalfoundry-2016-is-it-finally-time-to-upgrade-your-core-i5-2500k That's probably the one I'm thinking of. I could have sworn somebody looked at 99th percentile frametimes across different memory speeds though. Maybe I'm conflating two different articles
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May 13, 2017 02:07
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Yeah it looks like they forgot to mark the watt symbol on that column
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Jul 11, 2017 23:28
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PerrineClostermann posted:How much torque can a motherboard typically handle? So much torque, the substrate twisted coming off the line
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Jul 14, 2017 17:56
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wargames posted:they use epyc layout but aren't 2 that are disable just junk dies that never worked and they need the space to be filled for stability? But supposedly amd is getting fantastic yields with zeppelin dies. Maybe the yields are *so* good they can afford to completely waste some dies?
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Jul 30, 2017 20:04
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Do even the xeons come with glue now? I can't imagine data center customers are happy with chips that run hot for completely avoidable reasons
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Jul 31, 2017 10:51
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Did anybody else notice the page number
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Oct 20, 2017 07:14
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Drakhoran posted:Alas, I'm but a youngling whose first Wintel machine was a 486 DX 33MHz. I'm probably one of the youngest people here, the first computer I ever used was when my father brought home a Pentium III 
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Oct 20, 2017 17:28
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SSE* were big because: 1) Apart from its vector instructions it introduced support for actual 32- and 64-bit floating point, instead of using the x87 80-bit floating point instructions for everything. 2) AMD decided that SSE2 should be in the base spec for AMD64, so now it's guaranteed that if you have a 64-bit professor you can use at least SSE2. Compile some floating point code with GCC in 64-bit mode and you'll find it emits SSE2 instructions. AVX doesn't have any of that going for it, so it's pretty much always going to be relegated to places like HPC and video encoding, where the problems can be easily vectorized and it's relatively easy to guarantee that the hardware support exists. For most game developers, they'd have to make it optional to avoid alienating a large part of the market who might have older CPUs, and then they'd also have to test this additional code path. Just not worth the effort.
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Oct 27, 2017 06:20
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MaxxBot posted:Not sure how practical it is but it sure looks cool. I get that the flourinert is vaporizing inside the box to draw energy away from the components, but how does it cool down enough to go back to liquid? Does the gaseous flourinert get run through a heat exchanger with the atmosphere?
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Nov 18, 2017 22:37
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crazypenguin posted:Yep. (Though for Civ V, the big problem is just lazy coding... they didn't care about load times at all. So much gameplay data is scattered about in a huge number of xml files that it's only a moderate exaggeration to say the load times are so long because the game is compiling itself every run. If they just cached that work, it'd literally be 1000 times faster.) It's funny how easy it is to fall into this trap. You think, I'll just have all the game data be kept in human-readable* text files that the game parses at startup. Then you keep adding more and more things that that system can control, and other people add things, and before you know it your game takes an entire minute to get itself to the main menu. * Yes yes XML is ugly and killed all of our parents but it's still human-readable compared to, say, a raw dump of a sqlite database
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Nov 23, 2017 02:01
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repiv posted:PC Perspective got some interesting results from their post-Meltdown storage benchmarks They don't say how many trials they ran. 10% is a lot but it could still be random chance. I've been feeling this way about a lot of benchmarking websites lately. I wish they'd do lots of runs and report confidence intervals
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Jan 7, 2018 19:18
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Shaocaholica posted:Is the 'K' designation supposed to stand for something? Seems like it came out so long ago I forgot if it was supposed to mean something. Overclockable
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Apr 22, 2018 05:58
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Shaocaholica posted:No I mean literally. Unless its supposed to be the 'k' in overclockable then thats hella dumb.  I don't believe it was ever meant to stand for a word, it's just a designation. O can't be used for anything because it looks too close to 0
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Apr 22, 2018 06:17
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Laslow posted:I like to think it's a reference to Honda K series engines that were popular in riced-out Civics. OK now AMD needs to make a JZ-series CPU that can handle 1000W
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Apr 22, 2018 21:17
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I get zapped by work hardware every day. Or it zaps itself and resets because somebody walked in the room. Dev boards have interesting gremlins 
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Apr 23, 2018 18:03
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GRINDCORE MEGGIDO posted:Dumb question: what is it about avx instructions that causes so much additional heat? They do a lot of work. An avx 512 operation could be multiplying 16 pairs of floats in parallel, thats going to light up a lot of silicon
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Apr 25, 2018 05:49
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Rastor posted:I would love to read a Jim Keller employment contract, I bet they're crazy at this point Someone earlier in either this thread or the AMD thread described one. You basically have to summon him from another plane using a ritual and then sacrifice some folks to get him to design a chip for you.
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Apr 26, 2018 16:09
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Palladium posted:Just the Intel's net profit increase alone is only 19x more than AMD's entire profit this quarter Boot time doesn't matter cuz the AI only needs to boot once to kill us all 
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Apr 27, 2018 04:32
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Or Intel could use some other TIM that's still safe but better than whatever crap they currently use. Or they could solder the drat heatspreader on. There's many options here
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May 4, 2018 05:05
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Question that maybe some folks in this thread could answer. I've been looking at setting up a server on the cheap and came across this motherboard: https://www.newegg.com/Product/Product.aspx?Item=N82E16813182967&cm_re=dual_xeon_motherboard-_-13-182-967-_-Product It seems like a great deal, but I noticed it takes RDIMMs. Do I have to use registered memory with this board? Could I use unregistered?
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May 4, 2018 23:22
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Paul MaudDib posted:Nope, you can also use LRDIMMs! Thanks for the info! How bad is the price premium for RDIMMs? I think I would rather avoid buying ddr4 ones, but I do have some ddr3 ones that I got for free that *might* function, so I could find a ddr3-based motherboard and use even older xeons instead..... Used xeons seem to be in ample supply. Threadripper is super cool and all but for a hobbyist looking to do everything on the cheap it seems hard to pass up a pair of 8 core xeons for a third the price of a 1950x
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May 5, 2018 10:19
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The v2 xeons are the last ones to use ddr3 right?
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May 5, 2018 18:33
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What's the context of this
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May 11, 2018 18:17
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BIG HEADLINE posted:I do wonder why to help get a partial handle on 86/8700K thermal issues, why they haven't released an xx50K variant that has the iGPU disabled. If the 8086K has that, I might bite early - but I keep hearing rumors that there might be 'surprising' news at Computex about Z390 and the 14nm+++ octacores. Is that really necessary? I can't imagine the iGPU draws very much power when not in use.
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May 15, 2018 02:38
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Sininu posted:How does memory latency affect performance? I read that it gets worse and worse with each DDR generation. It's not actually getting worse and worse, it's staying roughly the same but since the numbers are expressed in terms of clock cycles and the frequency is increasing the latency numbers appear to get bigger
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May 18, 2018 00:25
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BangersInMyKnickers posted:If you're in a position to be targeting these specific branches of the AVX instructions, then odds are you using some specialized software that you own on top of large, consistent hardware platforms. Figure out what instructions your specific hardware supports, compile to target that, run it until the next hardware refresh. For standard commercial software, they're just going to target those inner three circles. Assuming any compilers other than icc even support all these avx variants... If you're targeting one of the more esoteric ones you might have to drop to assembly.
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May 25, 2018 16:49
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Methylethylaldehyde posted:Imagine if the 25 year old Best Buy geek squad employee you openly loathed every time you had to interact with him made hundreds of thousands per year talking about technology. Have you considered being a little nicer to service workers
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Jun 6, 2018 21:26
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Combat Pretzel posted:Maybe I'm not seeing it, but what's wrong with that RAID config? It's like RAID10, but instead of mirrors, it's arrays with parity. It's aptly called RAID50, too. So to be exact it was a windows storage spaces stripe across three hardware raid 5s, each on it's own raid controller. Then one of the controllers died in a way that wasn't recoverable just by swapping in a replacement, so they lost all the data, until a data reconstruction company managed to rebuild it. Each controller was a completely non-redundant failure point, with a catastrophic failure mode.
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Jun 6, 2018 23:14
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L33t_Kefka posted:Ok I laughed way too hard at this, Shocking Interview with Intel Engineer about 28-Core 5 GHz CPU (not really) Lmao
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Jun 8, 2018 08:06
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The R in CFL-R already stands for refresh right?
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Oct 21, 2018 06:30
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Kerbtree posted:Question: do modern CPUs still have a full set of all the instructions for 8/16-bit software? Every modern x86_64 CPU actually starts out running in real mode on power-up, and then the OS is responsible for telling it to switch to protected mode or long mode
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Jul 23, 2019 00:00
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