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Spite posted:Similar to why no one has a good solution for dynamically switching between an integrated GPU and a discrete one on the fly based on workload - you have to be able to assume the rest of the system is playing nice, which it most definitely is not. Don't some of the macbooks do exactly this?
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Jan 3, 2011 08:34
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Alereon posted:Anandtech just posted another article with even more details of the defect. Due to a design error, part of the PLL for the SATA300 ports is receiving too much voltage, leading to it burning out. This failure will occur over time, and will be accelerated by increased voltage and/or temperature. I'm not sure I get the explanation. Why would you bias a logic transistor? Generally the gate of a logic transistor is going to be at 0 or the supply voltage (ignoring the leakage from the previous stage) so I don't see where bias comes in. Also, shouldn't large blocks of the chip have the same supply voltage and same gate oxide thickness?
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Feb 1, 2011 03:31
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grumperfish posted:I don't see how the transistor technology would prevent them from using solder, wouldn't the top of the chip still just be a thick layer of silicon nitride?
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Apr 27, 2012 18:24
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Panty Saluter posted:So what are "foils" and why are we ridiculing them? Guessing it's a fabrication term, maybe something to do with masks from way back when? Google isn't coming up with much.
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Jun 17, 2015 00:34
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Anime Schoolgirl posted:It moves to 'loud explosion' In terms of number of chips shipped, samsung's 14nm seems to have ramped faster than intel's, although Intel is supposed to be smaller. Considering that Intel has delayed 10nm to "I dunno 2017 or something" and is heading into layoffs, meanwhile Samsung is fabbing most of the chips used in the sexiest and fastest growing market (high end smartphone soc), Intel is probably not going to be the leader in process tech going forward. Which seems crazy, intel's lead in process tech has lasted a long rear end time, but all things must end.
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Jun 24, 2015 17:40
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japtor posted:Hopefully they get inspired by the old GPU boxes, like have some monk meditating with a bunch of video gamey poo poo flying out of his head. Sadly, I can't find a picture of the 3D Nuclear Pope XL box.
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Aug 4, 2015 01:29
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japtor posted:Oh and a real edit re: a post on the last page, was 3D Nuclear Pope XL a real GPU or just a joke? Cause I've heard that name before but don't remember. It was a photoshop done by an SHSC poster way back in the day
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Aug 4, 2015 19:53
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Twerk from Home posted:Given that the non-OC parts also have a 65W TDP instead of a 95W one, the -K parts could end up being overall inferior this generation. Did I misread the charts or is the 6700k consuming a fair bit more power than the 4790k at the same clock speed? 2 years of development and intel's 14nm is still mediocre
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Aug 5, 2015 17:56
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Seamonster posted:That it may be but...aren't the only other 14nm chips in the mobile space? I mean thats not alot to go on... That's what I mean. So far Intel have been the only ones to try to create high power chips on the 14/16 node. The meh results don't bode well for the other players, since Samsung and tsmc will likely both be focused on the low power process corner. Hopefully tsmc's 16FF+ is decent for big chips, because GPUs have been stuck on 28nm for a long time
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Aug 5, 2015 18:34
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Fuzzy Mammal posted:Idf keynote summary looked hella lame. Did I overlook anything? Xpoint in consumer products in 2016 is cool
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Aug 18, 2015 19:54
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A decent article on how the mobile SoC is becoming the focus of the industry over the high-performance CPU: https://medium.com/@magicsilicon/how-the-soc-is-displacing-the-cpu-49bc7503edab Given Intels delays on the 14nm node and them pushing out their 10nm node, I wonder if samsung or tsmc will beat intel to shipping 10nm node chips in volume.
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Nov 22, 2015 22:17
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A guy wrote some words about why intel moved away from soldered heat spreaders (and apparently tried soldering a CPU himself, with success) http://overclocking.guide/the-truth-about-cpu-soldering/ The reddit thread linked to a paper with more info as well: http://iweb.tms.org/PbF/JOM-0606-67.pdf
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Nov 25, 2015 05:46
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https://www.reddit.com/r/hardware/comments/44k218/intel_disables_tsx_transactional_memory_again_in/ Intel has quietly stopped advertising TSX support on a bunch of Skylake processors.
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Feb 7, 2016 06:24
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Tab8715 posted:Intel Launches Cloudbooks More specifically, they're announcing new Atom cores to be available in the 2nd half of 2016
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Apr 16, 2016 12:40
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Palladium posted:http://www.hardocp.com/news/2016/07/10/motherboard_players_see_2030_drop_in_2q16_shipments/ Doesn't Asia own asrock? Or do I have it backwards and were they a spinoff?
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Aug 21, 2016 05:08
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Lube banjo posted:is it safe to say that we will not see any great performance gains until the 7nm graphene chips become available? The 7nm process generation at TSMC, Samsung, and Global Foundries will all be based on standard FinFet silicon techniques, with the main difference being scheduling, the exact PPA (power, performance, area), and whether and how they plan to being in EUV lithography to partially replace standard 193nm immersion lithography. TSMC isn't planning on any EUV for their 7nm node, while the other two are, however, TSMCs 7nm generation process is scheduled to hit production a lot sooner than the other two, probably in time for a 2018 apple product. I don't know if Intel has given many details of their 7nm process (which probably won't come until 2020 or 2021 at their current pace) but I don't think anyone is expecting any exotic silicon replacements. Gate-all-around transistors, III-V transistors, quantum-well FETs, and some other things are vaguely on future roadmaps, but I haven't heard of any use of graphene happening on the next few nodes.
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Nov 21, 2016 00:22
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An interesting talk from intel looking at moore's law going into the future: https://player.vimeo.com/video/164169553
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Jan 8, 2017 02:32
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silence_kit posted:And there's the issue that because of the heat dissipation constraint, you are obligated to design your circuits with a lower activity factor if you want a higher density at the same speed. I suspect he may not be accounting for those factors when he presents the cost/function plot, and is presenting the cost/function plot as if the entire computer chip were a single adder circuit, without having many of the real constraints of a real computer chip. I think that's why he was so focused on the need to move to lower energy devices. It's not primarily about laptop battery life or anything, it's about keeping power density below surface-of-the-sun levels. Your point about interfaces and interconnect scaling is a good point though.
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Jan 8, 2017 21:34
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BurritoJustice posted:To be fair, there is already a microcode update that fixes it. Definitely a good reason to keep abreast of UEFI updates for your board though. it seems to just hit the kill bit for that particular optimization, but I think that's pretty typical for microcode fixes
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Jun 26, 2017 19:46
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