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orange juche posted:There's still a year and change between now and Zen, which means several Intel iterations and improvements on their tick/tock scaling. I won't hold my breath for AMD to even get close to passing that momentum. Intel has a bit of a mess with their "Broadlake" thing happening... AMD could make some progress till then. I presume someone realised that Bulldozer is poo poo and started work on fixing the said poo poo a while back, not just now. Maybe, just maybe this thing has been in the works for a long while now?
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Oct 7, 2014 00:55
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How does POWER work for single-threaded performance compared to Intel?
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Oct 7, 2014 04:47
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JawnV6 posted:We'll never know until there's Arduino-level tools for playing with new architectures. You can get quite far with FPGAs. It isn't quite as simple, but considering you are designing a loving CPU... (Two cool "actually used in the wild" ISA CPUs implemented here. Next up: Coldfire!)
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Oct 10, 2014 05:12
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SwissArmyDruid posted:Well, this could either be absolutely brilliant, or complete folly for AMD. It's hard to tell at this point. Sounds a lot like hyper-threading on CPU scale to me. I can imagine this making more threads runnable. I cannot see how this would give you better single-threaded performance, especially not with such a large speedup as is claimed. And single-thread is where the battle for the desktop is being won. EDIT: Maybe it is like dynamic vectorization/recompilation and GPU offloading? Hello, Transmeta.
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Nov 4, 2014 22:21
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Yeah. Take something single threaded and make it run in parallel where possible. Neat idea, even though I remain a skeptic. I do note they measure the speedup in instructions per core per cycle. What is the clock speed then? EDIT: Look at their pipeline. 11 stages. Out of this, the execute phase takes one stage, unless it is a long latency or memory operation in which case you have two stages. That's either a lot of work done in a stage or a very simple ISA where you need a lot of instructions to do something. For this to run x86, this will run either very slowly clockwise, or will have enormously long pipelines when running fast. EDIT2: Unless they manage to do their data accesses before they hit the execute stage, during dispatch or something. Might be possible, I guess. No Gravitas fucked around with this message at 22:57 on Nov 4, 2014 |
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Nov 4, 2014 22:34
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Longinus00 posted:The term you're looking for is Speculative multithreading. Funny, I should have heard about it. I also adore the fact that the article has about five times as much space dedicated to citations than to content. JawnV6 posted:Can't always know what memory's necessary before the prior instruction's out of execute I know, I was just trying to come up with some way to make it work. I guess I'd really like this to succeed, but I just don't see how it could work in the end.
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Nov 5, 2014 19:33
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I am not a book posted:If I wanted to justify myself to goons more than I had to, I'd post in E/N. The fact that fanboys exist doesn't mean that everyone who wants to buy AMD is a 1337 haxxor. We aren't fanboys, we just have a functioning brain and can read benchmarks. And being nice guys, we warn people who don't have one of those two traits. If you don't put in more effort than a single sentence, we will be cautious and assume you may lack one of them. We like to play it safe.
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Dec 30, 2014 05:04
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Lord Windy posted:In this thread, does anyone explain the problems that Bulldozer had? I am interested and want to read up on it. http://www.agner.org/optimize/microarchitecture.pdf Section 15.19 is of interest to you. Long story short: poo poo instruction decode in early models, poo poo execution unit balance which harms integer-based performance, long latencies for many operations, long pipelines causing problems with mispredicted branches aaaaaand finally some issues with caches (more severe on some models).
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Mar 20, 2015 12:09
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Truga posted:Well, it makes sense, kinda? If you spent a couple hundred on cpu silicon alone, you're probably getting a separate GPU anyway. If nothing else, it should make cooling more efficient? I wonder if it would be possible to just stick in copper plates into the CPU to wick heat away. Usually we get a dead/disabled core, but if we could instead of that have on-chip heatsinks. (I know nothing of this, just musing aloud.)
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Apr 29, 2015 22:50
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JawnV6 posted:You don't know where the dead core will be ahead of time. Taking the time and effort to locate one is difficult enough, having a second op to remove that silicon and put something else in would be horrendous for efficiency. Oh, I know that. But you could just pick some cores and replace them with metal instead of even attempting fabbing them for cores. You would alternate core metal core metal core. Yes, your yields would suck. But would it actually help to get heat out of the chip? With shrinking processes you could probably just have them in between the cores anyway. I always see the chip crammed on chip photograps, but maybe some metal spacers would help wick the heat out?
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Apr 30, 2015 19:47
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Sidesaddle Cavalry posted:In which I got totally wrecked by a fake presentation slide the other day and the single platform is actually called AM4. Assuming no decrease in clock rates?
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May 6, 2015 21:55
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AMD CPU and Platform Discussion: New Zen platform might actually be good!
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Aug 15, 2015 06:59
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Twerk from Home posted:GPUs have exciting stuff on the horizon, but CPU gains look to be slow and incremental for a couple years at least. I'm rooting hard for AMD to make a return to server competitiveness and make Intel blink a little bit with Xeon pricing. The E5 and E7 chips look to be their fat moneymakers right now, and if AMD can make some 14-20 core haswell competitive chips and is able to find a way to sell them for ~$1k - $1500, they're in business. Of course you are then competing against this deal, of 600$ shipped for 16 cores spread across two CPUs, 128GB RAM and a motherboard: http://www.natex.us/product-p/s2600cp-cpu-128gb-12800.htm
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Apr 25, 2016 23:30
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Arsten posted:So, in basics, the minimums I'm seeing are the minimum required energy to keep the processor "on" so if they cut the processing speed to 500Mhz from the current idle of 1Ghz, they use the same amount of power in both states because it's keeping one segment of the core alive at the lowest power level available? Some technologies require a minimum clock rate, for example: https://en.wikipedia.org/wiki/Dynamic_logic_(digital_electronics)
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Jun 11, 2016 07:04
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Wistful of Dollars posted:You should write it and submit it. I'd be game to do this. Can someone provide convicting pictures of "internal" slides we could leak?
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Dec 21, 2016 00:18
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repiv posted:IBM has some nice illustrations of on-chip watercooling, it would be a shame if someone were to photoshop them into AMDs slide template I spiced it up a bit. https://imgur.com/a/ciyas
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Dec 21, 2016 01:07
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My favourite bit is the Chernobyl reference. https://en.wikipedia.org/wiki/Chernobyl_liquidators
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Dec 21, 2016 11:35
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May I interest you fine folks in crashing Ryzen machines even from a VM? https://www.techpowerup.com/231536/amd-ryzen-machine-crashes-to-a-sequence-of-fma3-instructions
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Mar 21, 2017 20:27
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BurritoJustice posted:The CPU-Z benchmark is inaccurate for Ryzen, as it was made with 256MB L3 cache in mind and the Ryzen has 512MB. Other than that, neat. It is amusing that your CPU gets four times the cinebench score of my stock 3570K. Cache sizes sure made a great leap forward since the morning, no?
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Mar 26, 2017 05:37
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| # ¿ Apr 29, 2024 10:48 |
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eames posted:AMD sale at newegg! This one is of the Piledriver architecture, so I'm not so sure about this.
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Mar 30, 2017 08:39
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