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SwissArmyDruid posted:Hm. The heatspreader has that weird rib in the middle... Cygni posted:either way, the whole thing is weird.
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Jul 27, 2017 18:17
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Oh man, I know we have made jokes in the thread, but if there turns out to be a way to turn TR into Epyc with a graphite pencil, I will be so happy. 
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Jul 27, 2017 18:23
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Looking over the R3 reviews... that R3 1300X looks like it is _the_ chip to get in that segment. edit: Wow, I take it back, I just looked at the pricing. $130 and no graphics silicon compared to the i3s? :hmmm: SwissArmyDruid fucked around with this message at 18:39 on Jul 27, 2017 |
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Jul 27, 2017 18:30
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There is no way AMD are plopping 2 extra dies onto a TR package. Barring some sort of strange technical limitation where they need to use 4 interconnects this is pretty ridiculous of a rumour.
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Jul 27, 2017 18:38
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SwissArmyDruid posted:Looking over the R3 reviews... that R3 1300X looks like it is _the_ chip to get in that segment. Street price on the R5 1400 is $135 right now, is hyper-threading worth $5?
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Jul 27, 2017 18:44
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Twerk from Home posted:Street price on the R5 1400 is $135 right now, is hyper-threading worth $5? Yeah, definitely.
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Jul 27, 2017 18:46
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Krailor posted:The quad vs octo channel memory between Threadripper and Epyc is a direct result there being half as many active dies on the chip. Each Ryzen die has 2 memory controllers resulting in dual channel memory access. If you have 2 active dies on a chip (Threadripper) each die can access two banks of memory simultaneously giving it 'Quad-Channel' memory access. Doubled again for Epyc to get 'Octo-Channel' memory access. A single core can't actually access more than two banks of ram at a time. Four dies. Die 1 and 2 are connected to memory. Say die 1 is rendered unfunctional, due to binning or what, so for instance die 3 does computing, but die 1 still does memory duty, since die 3 isn't hooked up to the right pins. Worst case being die 1 and 2 doing memory, and die 3 and 4 doing computing. The alternative variant being each die doing a single channel of memory and only two dies of the four doing computing. --tl,dr: The dies on the quad memory channel pinouts do memory IO, and computing is done by the best bins on the package and get memory access via IF, if not directly hooked up. Combat Pretzel fucked around with this message at 18:50 on Jul 27, 2017 |
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Jul 27, 2017 18:47
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Combat Pretzel posted:
Based on ServeTheHome's Epyc tests, having to hit IF for the memory calls would have a ~40% hit on latency and ~50% hit on bandwidth vs each cores integrated controller. X399 only supports 4 channel memory, so only 2 of the dies can have active memory controllers. The 2 extra cores on the engineering sample really are completely vestigial. Im putting my chips in the "they just reused Epycs as engineering samples and production models will only have 2 dies" pile, because its the only thing that makes sense to me. At least weve got somethin weird to talk about!
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Jul 27, 2017 18:57
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Risky Bisquick posted:There is no way AMD are plopping 2 extra dies onto a TR package. Barring some sort of strange technical limitation where they need to use 4 interconnects this is pretty ridiculous of a rumour. It doesn't make sense not to test the chips before they are packaged, too. They aren't going to be just sticking them on a package and testing it afterwards and having enough post - packaging failures to make it worthwhile. IMHO.
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Jul 27, 2017 19:17
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AMD is now selling the Wraith Max xXxRGBxXx cooler.... for 60 dollars http://www.tomshardware.com/news/amd-ryzen-wraith-max-cooler,35098.html
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Jul 27, 2017 19:47
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Considering they test chips before they leave the wafer...
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Jul 27, 2017 20:20
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Watermelon Daiquiri posted:Considering they test chips before they leave the wafer... See, that's what I assumed, so none of this makes sense, unless they're failed dies put in place just to keep the heatspreader level or something weird.
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Jul 27, 2017 20:23
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HalloKitty posted:See, that's what I assumed, so none of this makes sense, unless they're failed dies put in place just to keep the heatspreader level or something weird. Single socket style, single interposer/package style, single soldering setup to work the kinks out of, all for the cost of whatever wasted/dead dies. From a process simplification standpoint, it could work.
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Jul 27, 2017 20:35
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Maybe they just wanted to get something out and an Epyc chip was at hand? Flashed the microcode to a threadripper and there you are.
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Jul 27, 2017 20:38
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Maybe they'll start a 32 core Threadripper line if all the 16s sell.
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Jul 27, 2017 20:44
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Has AMD said if TR cores are disabled symmetrically across all cores a la R5, or are we looking at potentially goofy-rear end core counts like 1/7/6/2?
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Jul 27, 2017 20:50
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ArgumentatumE.C.T. posted:Maybe they'll start a 32 core Threadripper line if all the 16s sell. maybe not 32 core but I'm sure we'll see 20/24 core Threadrippers with 7nm
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Jul 27, 2017 20:57
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Ryzen Threadripper II, 64C/128T
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Jul 27, 2017 21:10
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MaxxBot posted:Ryzen Threadripper II, 64C/128T 
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Jul 27, 2017 21:12
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HalloKitty posted:See, that's what I assumed, so none of this makes sense, unless they're failed dies put in place just to keep the heatspreader level or something weird. It could be like the RX480, where they shipped all early units with 8GB of VRAM and just artificially capped some units at 4GB. Later on they started making actual 4GB cards. Similarly they might phase out the quad-die Threadripper and introduce a native two-die design later.
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Jul 27, 2017 21:18
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https://www.youtube.com/watch?v=Ni9MdFNQCCE lmfao. brb going to see threadripper at lollapalooza
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Jul 27, 2017 22:15
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"PCIe" is a registered trademark? wat?
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Jul 27, 2017 22:17
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Combat Pretzel posted:"PCIe" is a registered trademark? wat? http://pcisig.com/sites/default/files/newsroom_attachments/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf Pretty much all standards are trademarked. That's how they control compatibility claims.
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Jul 27, 2017 22:21
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Combat Pretzel posted:"PCIe" is a registered trademark? wat? Probably the last major one that wasn't is ISA, and then only because that was a retroactive name applied after it'd already been in use for several years with no real name besides "the expansion bus IBM PCs use"
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Jul 28, 2017 00:00
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MaxxBot posted:Ryzen Threadripper II, 64C/128T Nice photoshop of the original xbox cpu!
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Jul 28, 2017 00:06
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NewFatMike posted:Bristol Ridge has been out with OEMs for like a year now though, hasn't it? https://www.scan.co.uk/shop/computer-hardware/cpu-amd/amd-a-series-socket-am4-apu-processors
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Jul 28, 2017 00:30
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inkwell posted:https://www.youtube.com/watch?v=Ni9MdFNQCCE  Hell yeah CPU division. Anime Schoolgirl posted:if the UK preorder pricing is anything to go by, the APUs will be AMD's 50-100 dollar range for the meanwhile Oh nice. That A12 isn't bad at 720p IIRC. Give me Raven Ridge already! I want to see the laptops! I want to make my SFF gaming boxes!
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Jul 28, 2017 00:39
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NewFatMike posted:
my laptop uses an A8 and works pretty drat well at 720p.
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Jul 28, 2017 00:54
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Freesync 2 monitors on laptops is going to dramatically improve laptop gaming too, I think. Good golly Ms. Molly, please give me a beefy APU, Freesync 2, IPS, 3:4, and an active stylus. I need it* Inasmuch as anyone needs a laptop when they have a beefy desktop.
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Jul 28, 2017 01:02
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Jul 28, 2017 01:12
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http://www.pcworld.com/article/3211409/computers/why-ryzen-threadripper-has-two-mysterious-chips.htmlPC World posted:So did AMD really waste two perfectly good "Zeppelin" dies? Nope.
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Jul 28, 2017 02:34
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repiv posted:http://www.pcworld.com/article/3211409/computers/why-ryzen-threadripper-has-two-mysterious-chips.html That's good. Intel would have just used more glue.
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Jul 28, 2017 02:36
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repiv posted:http://www.pcworld.com/article/3211409/computers/why-ryzen-threadripper-has-two-mysterious-chips.html Wierd, but that kinda makes sense, if the rest of the threadripper package is based off of Epyc. Remember that shot of the IF traces between the die (and how two of the dies were mirrored)? Makes sense if they replaced the mirrored dies with blanks; thered just be the one diagonal IF bridge between top left and bottom right instead of whatever multi layer thing they were doing to get single hops between all four dies on epyc. Im totally talking out of my rear end here; but assuming it was using the same PCB as epyc would that mean that tr4 has a ton of unused lands/pins? Also i gotta wonder what that means for cooler design if you've got hotspots on opposite corners of the ihs rather than near the center...
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Jul 28, 2017 03:37
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what if the spacers are completely defective zeppelin dies 100% yields 
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Jul 28, 2017 04:04
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I imagine using only one socket makes it simpler for the board designers and the unfortunate people who have to design trace paths for this poo poo. Plus it's a great way to use completely wasted dies that aren't even good for Ryzen 3s.
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Jul 28, 2017 04:08
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Anime Schoolgirl posted:I imagine using only one socket makes it simpler for the board designers and the unfortunate people who have to design trace paths for this poo poo. Unfortunate? You know Asrock engineers live for this poo poo, they would have gone insane years ago otherwise. 
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Jul 28, 2017 04:11
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isndl posted:Unfortunate? You know Asrock engineers live for this poo poo, they would have gone insane years ago otherwise.
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Jul 28, 2017 04:12
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If you gave Asrock engineers an infinite amount of money you'd have an endless cascade of weird poo poo like 5-6 people would buy. Like Imagine ASRock partnering with Nvidia to bring out a socketed Tegra line of chips.Anime Schoolgirl posted:They're in an entire different league, what with the micro-stx project that isn't going to work with about 86% of MXM cards because there was no standard for that Knowing Asrock, they'll standardize MXM, and then proceed to become an AIB for MXM GPUs. They'll then buy up as much old stock of MXM cards as possible and then transfer all the chips to the new standardized PCB. But seriously I'll buy their STX form factor if it comes in AM4 though because that shits perfect for AMD APUs. I have no interest when it's just Intel GPUs though because while it's a lot of CPU horse power the GPU is laughably bad.
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Jul 28, 2017 04:23
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NewFatMike posted:Raven Ridge allegedly spotted today, as well. Whoa, back up a sec here. Is this with just straight system RAM? All Iris Pro parts have eRAM built in-die, right?
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Jul 28, 2017 04:44
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I can't discern anything besides 4C/8T and Vega GPU architecture, but I'm glad somebody else got a little hype over it. I'm too thirsty for Raven Ridge news for that little story to be ignored.
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Jul 28, 2017 05:05
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