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PC LOAD LETTER posted:They did do a on die GDDR5 for some of the next to last or last gen AM3 APU's I believe but they never actually added the GDDR5 to the package. Its unknown why. Elpida was going to manufacture lpddr5 but went bankrupt instead.
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Oct 31, 2018 09:01
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No reason not to try again I suppose, LPDDR6 is even more feasible than LPDDR5.
EmpyreanFlux fucked around with this message at 14:37 on Oct 31, 2018 |
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Oct 31, 2018 14:32
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Arzachel posted:Elpida was going to manufacture lpddr5 but went bankrupt instead.
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Oct 31, 2018 23:52
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I recently got the dell inspiron 2 in 1 with the r5 2500u, and while I can't speak to color accuracy, I can say that the battery life is the only real limiting factor. I get 3.5hrs near minimum brightness watching YouTube videos. It's built drat solidly in comparison to most 600 dollar laptops, the TouchPad is fine, the screen is fine, the speakers are loud as hell without much if any distortion. It games way better than any integrated solution should, but it's still not anywhere approaching a powerhouse. It feels like it has way more zip than my ~3 year old lenovo of the same form factor, but since the only real differences between them are the processor and the age, I'm going with its because of a clean windows install.
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Nov 1, 2018 00:10
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AMD will hold an event called "Next Horizons" on Nov 6th. The original Ryzen brand was launched at an event called "New Horizons" in Dec 2016. Looks like some Zen 2 details are coming soon. https://www.anandtech.com/show/13538/amd-investor-relations-next-horizon-november-6th
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Nov 2, 2018 01:31
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Cygni posted:AMD will hold an event called "Next Horizons" on Nov 6th. YAY!  Maybe I'll be able to finally ditch my aging 2500K rig soon.
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Nov 2, 2018 02:47
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spasticColon posted:YAY! To avoid disappointment calibrate your values of "soon" to "some time next year". The rumors that have been circulating around for a while now are that AMD will launch Zen 2 on their EPYC server lineup first in the first half of the year, with consumer parts coming in the second half of the year. I'm in the same boat as you, with a 3570K.
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Nov 2, 2018 03:30
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Looking forward to quite likely replacing my X5660 with a 3700 when Zen 2 launches, if they can get within a few percent of 9900K performance for less heat/cost .
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Nov 2, 2018 17:11
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AMD Next Horizon event has been goin for a bit, I'm just now tuning in   Live stream: https://www.youtube.com/watch?v=GwX13bo0RDQ
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Nov 6, 2018 18:51
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Zen2 has full-rate AVX apparently, there goes another one of Intel's selling points.
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Nov 6, 2018 18:54
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7nm CPU chiplet dies with 14nm IO die.
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Nov 6, 2018 19:02
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Second generation Infinity Fabric? Hmm. Also slide says doubled core density? (Still watching.) --edit: Eeeeeeeeee, new CPU again next Summer/Fall.
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Nov 6, 2018 19:25
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All as was prophesied.
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Nov 6, 2018 19:27
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Holy poo poo, I didn't think they'd actually do the IO chip+ chiplets. I thought for sure it was fantasy. Threadripper 3 is going to be pants-on-head bananas.
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Nov 6, 2018 19:36
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Is that stuff on an interposer, or do the chiplets connect via PCB traces? Or is the IO die the interposer?
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Nov 6, 2018 19:37
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Combat Pretzel posted:Is that stuff on an interposer, or do the chiplets connect via PCB traces? Or is the IO die the interposer? Interposers have circuit traces, and the IO die is not an interposer. I think they're all communicating via the new infinity fabric they announced.
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Nov 6, 2018 19:42
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Combat Pretzel posted:Second generation Infinity Fabric? Hmm. loving hail satan... I hope that means 16 cores/32 threads in mainstream because then I might actually have enough threads to satisfy the rust compiler. Edit: 2x the physical cores per socket, double confirmed. Anarchist Mae fucked around with this message at 19:46 on Nov 6, 2018 |
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Nov 6, 2018 19:44
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NewFatMike posted:Holy poo poo, I didn't think they'd actually do the IO chip+ chiplets. I thought for sure it was fantasy. Is this good or bad? I don't know enough about chip design. I'm interpreting chiplet to chip as basically daughterboard to motherboard only since it's on the CPU it's not user changeable. I'm assuming I'm wrong though.
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Nov 6, 2018 19:46
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NewFatMike posted:Holy poo poo, I didn't think they'd actually do the IO chip+ chiplets. I thought for sure it was fantasy. Saaaaaame, thought we were gonna hey 1 more symmetrical MCM generation before he chiplet future, but nope! AMD going big risk big reward. This will be fun.
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Nov 6, 2018 20:05
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pixaal posted:Is this good or bad? I don't know enough about chip design. I'm interpreting chiplet to chip as basically daughterboard to motherboard only since it's on the CPU it's not user changeable. I'm assuming I'm wrong though. IO, memory controllers, voltage regulators, and other uncore stuff don't scale well with process shrinks. It's good in that it will make the product more affordable. The way these things are connected is far faster than how ram and a cpu is connected, though this design will still introduce latency.
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Nov 6, 2018 20:09
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pixaal posted:Is this good or bad? I don't know enough about chip design. I'm interpreting chiplet to chip as basically daughterboard to motherboard only since it's on the CPU it's not user changeable. I'm assuming I'm wrong though. This is probably good. There's a possibility that it exacerbates some latency issues that we're seeing on existing Zen platforms (like Windows being crappier than Linux at the WX Threadripper SKUs) and there will likely be some new issues as with any new computing platform. All that said, there will probably be some buck loving wild performance metrics relative to Intel - especially with things like CPU based rendering (which Ryzen is already super good at). Say 7nm just gives us the 15% clock increase and no other improvements are made. That essentially puts Zen cores at parity with Skylake cores. Everything else is just gravy, and I'm optimistic to be drowning in gravy.
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Nov 6, 2018 20:18
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Truga posted:I have it on pretty good authority that epyc2 is going to be 8x8 cores and also a +1 something else. Is there anything that +1 thing could be besides a gpu? 
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Nov 6, 2018 20:25
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Epyc summary: - 64/128 threads Zen 2 cores per socket - 2x performance per socket, 4x floating point performance per socket - Compatible with current motherboards boards - New boards have PCIe 4.0 and forwards compatibility with "Milan" - 8x 8 core 7nm die - 1x IO 14nm die
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Nov 6, 2018 20:26
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So this event was just for data center/server stuff right? Nothing concrete for consumer level (2x00 series successor), just inference that some of this tech may trickle down to consumer level?
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Nov 6, 2018 20:29
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2x Intel Xeon 8180m vs 1x Epyc "Rome" prototype No frequency details, air cooled, not overclocked.
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Nov 6, 2018 20:31
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MH Knights posted:So this event was just for data center/server stuff right? Nothing concrete for consumer level (2x00 series successor), just inference that some of this tech may trickle down to consumer level? The likelihood is that the Zen 2 core is the same all through the product stack like it is now. I would also bet on some Threadripper SKUs being exactly the same as some EPYC SKUs with some feature limitations (e.g. fewer memory channels available). Beam me up, Dr. Su. I want to rip and tear those threads.
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Nov 6, 2018 20:36
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MH Knights posted:So this event was just for data center/server stuff right? Nothing concrete for consumer level (2x00 series successor), just inference that some of this tech may trickle down to consumer level? Yeah, at this point we know only that they have 8 core chiplets, which is likely going to be used for Ryzen too. I suspect that the 14nm IO die would be different between Epyc and Ryzen, it really wouldn't make sense to try and cram something capable of handling 64 cores into a Ryzen sized package. Apparently there's more to come after lunch today, demos and showcases. Maybe if we're lucky they'll have something consumer tucked away in a corner.
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Nov 6, 2018 20:39
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sincx fucked around with this message at 05:50 on Mar 23, 2021 |
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Nov 6, 2018 20:43
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sincx posted:How are they linking the die to the chiplet? Aren't interposers expensive? This arrangement will not likely be used for consumer parts: IO stuff is still on the chiplets, just fused off to increase yield and clock potential. So latency on AMDs single die CPUs won't necessarily change unless they up the core count. Intel's ring bus/mesh whatever it's called has its own latency problems, so whatever faults there are here should be taken in that context.
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Nov 6, 2018 21:19
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One chiplet (CCX) has 8 cores and includes I/O? I assume this would be a very significant latency improvement for their 6-8 core consumer parts and Threadripper would scale up to 64 cores if it retains the current layout?
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Nov 6, 2018 21:26
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Ya, we have a source on chiplet having the IO? Single CCX for 8/16 in consumer stuff is a pretty big deal. Makes anything less probably very cheap to produce. Heat to surface area is going to be pretty high on those. Wonder if the chips have higher temperature tolerance.
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Nov 6, 2018 21:30
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eames posted:One chiplet has 8 cores and includes I/O? In the case of Rome, functionally no. The reason I said it is still likely there but fused off is because there is no way AMD spent $600-$750 million for two Zen2 photomasks just to have one that omits integrated IO. It would also ruin how they bin, with server parts that don't make the cut becoming consumer Zen CPUs. Rome's IO will be handled entirely by the 14nm IO core and connected via infinity fabric to each 7nm chiplet.
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Nov 6, 2018 21:33
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I wanna see one of those chiplets on a GPU package together with 16GB of HBM3 for an unholy reverse APU
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Nov 6, 2018 21:38
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3peat posted:I wanna see one of those chiplets on a GPU package together with 16GB of HBM3 for an unholy reverse APU Maybe that will be the PS5 Pro.
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Nov 6, 2018 21:56
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Oh heh.
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Nov 6, 2018 22:16
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Huh, wonder if that's still going to be soldered. If not invest in TIM now before it's too late! 
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Nov 6, 2018 22:18
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Yudo posted:In the case of Rome, functionally no. The reason I said it is still likely there but fused off is because there is no way AMD spent $600-$750 million for two Zen2 photomasks just to have one that omits integrated IO. It would also ruin how they bin, with server parts that don't make the cut becoming consumer Zen CPUs. Rome's IO will be handled entirely by the 14nm IO core and connected via infinity fabric to each 7nm chiplet. More likely the chiplets are all designed to use the same 14nm IO chip interface, because 7nm is loving bonkers expensive to make, so you use it on the smallest possible part you can. The difference between Epyc and Ryzen will most likely be at the 14nm IO chip level, where Eypc has the fat boy 8 channel 8 chiplet controller, and Ryzen has a much smaller, cheaper, and more power efficient two channel memory controller and 2 chiplet Infinity bus. Masks at 14nm aren't THAT expensive, and the cost savings going from 100 parts per wafer to 250+ parts per wafer can offset the mask costs in a hurry. Edit: It also means they can aggressively bin every single chiplet for frequency and voltage, since they're 100% standard across the entire product stack. Methylethylaldehyde fucked around with this message at 22:40 on Nov 6, 2018 |
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Nov 6, 2018 22:37
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Combat Pretzel posted:Oh heh. sweet lord forgive us
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Nov 6, 2018 23:01
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MH Knights posted:So this event was just for data center/server stuff right? Nothing concrete for consumer level (2x00 series successor), just inference that some of this tech may trickle down to consumer level?
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Nov 6, 2018 23:05
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Methylethylaldehyde posted:More likely the chiplets are all designed to use the same 14nm IO chip interface, because 7nm is loving bonkers expensive to make, so you use it on the smallest possible part you can. The difference between Epyc and Ryzen will most likely be at the 14nm IO chip level, where Eypc has the fat boy 8 channel 8 chiplet controller, and Ryzen has a much smaller, cheaper, and more power efficient two channel memory controller and 2 chiplet Infinity bus. Masks at 14nm aren't THAT expensive, and the cost savings going from 100 parts per wafer to 250+ parts per wafer can offset the mask costs in a hurry. What you are saying makes a huge amount of sense and is indeed the more likely scenario. Also, point well made about how nuts doing IO at 7nm would be. The only thing I will quibble with you over is the cost of masks: at the advent of the process, the mask for a complex 28nm chip could run as much as $150 million; with multi-patterning at 14nm, that cost is going to scale exponentially. So while I may be overstating it, I still am going to assume that AMD will go out of their way to minimize how many they need. Let's all hope TSMC's 7nm works as advertised, or next year will suck more than it must.
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Nov 6, 2018 23:53
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