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Perplx
Jun 26, 2004


Best viewed on Orgasma Plasma
Lipstick Apathy
I know not fair but the passive m1 handily beats the new intel space heater at JavaScript benchmarks, also you can’t seem to buy a 7nm anything right now but you can get 5nm iPhone and MacBooks easily.

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DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

Cygni posted:

Frankly can’t see why anyone wouldn’t just get the $350 10850k over the Rocket Lake parts if that’s true.

As a DIY, yeah, I agree. But it'll find its way into a ton of OEM / pre-builts regardless of actual performance.

Gucci Loafers
May 20, 2006

Ask yourself, do you really want to talk to pair of really nice gaudy shoes?


Alder Lake is not only 10nm but also a completely new architecture with DDR5 and PCI-Express 5.0.

I would think it'd have to be at worst a little faster?

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

Crosby B. Alfred posted:

Alder Lake is not only 10nm but also a completely new architecture with DDR5 and PCI-Express 5.0.

I would think it'd have to be at worst a little faster?

Remember that DDR5, at launch, is not expected to be much faster in actual use vs high end DDR4. PCIe 5 is almost entirely pointless at this juncture and will provide zero actual speed benefit to Normal Users--PCIe 3 is enough for any current GPU and single SSD. A second SSD, even on PCIe 3, is unlikely to see actual speed limits in real use. PCIe 4 removes the limits even in benchmarks. PCIe 5 is for the server bros.

10nm...we'll see.

Paul MaudDib
May 3, 2006

TEAM NVIDIA:
FORUM POLICE

DrDork posted:

Remember that DDR5, at launch, is not expected to be much faster in actual use vs high end DDR4. PCIe 5 is almost entirely pointless at this juncture and will provide zero actual speed benefit to Normal Users--PCIe 3 is enough for any current GPU and single SSD. A second SSD, even on PCIe 3, is unlikely to see actual speed limits in real use. PCIe 4 removes the limits even in benchmarks. PCIe 5 is for the server bros.

10nm...we'll see.

yet again, that's not true, DDR5 moves to quad channel (smaller channels, but it can have more independent requests in-flight at once) and is a pretty significant increase in MT/s, DDR5 JEDEC specs are beating top-binned DDR4 kits and DDR5 JEDEC is absolutely slamming the 3200-3866 kits that most people actually buy. Actual DDR5 performance kits will have similar latency to what the current performance DDR4 kits do so that won't be an issue.

if you want a real-world measure, AMD is now talking about a "Zen3+" which will be Zen3, on AM5, with a DDR5 IO die. They expect that to get a 4-7% IPC improvement and almost all of that will come from the better memory. And that's an architecture that isn't specifically designed for it, just has a DDR5 IO die slapped onto it.

https://www.techpowerup.com/278321/amd-zen-4-reportedly-features-a-29-ipc-boost-over-zen-3

like, is it going to be a whole architecture's worth of gains? no, of course not. Does it increase IPC by a fairly large chunk, as far as a single optimization goes? yes, memory does matter a lot, this idea that people have that because you're not constantly slamming into the bandwidth bottleneck that consumer workloads/gaming are completely unaffected by memory performance is false.

Paul MaudDib fucked around with this message at 20:44 on Mar 6, 2021

movax
Aug 30, 2008

DrDork posted:

Remember that DDR5, at launch, is not expected to be much faster in actual use vs high end DDR4. PCIe 5 is almost entirely pointless at this juncture and will provide zero actual speed benefit to Normal Users--PCIe 3 is enough for any current GPU and single SSD. A second SSD, even on PCIe 3, is unlikely to see actual speed limits in real use. PCIe 4 removes the limits even in benchmarks. PCIe 5 is for the server bros.

10nm...we'll see.

The main advantage I see for the faster and faster PCIe specs for consumers is just needing less lanes and therefore less pins to hit target speeds. Lot of stuff (i.e. 10 GbE NICs) eating 2-4 lanes when they could eat 1-2. We don't need x16 4.0 / 5.0 links on the desktop but having smaller slots / more M.2 slots for various devices / more ThunderBolt / etc could be pretty useful. Storage especially -- that stuff is almost always physical lane limited or physical case-size limited, not CPU limited.

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

Paul MaudDib posted:

yet again, that's not true, DDR5 moves to quad channel (smaller channels, but it can have more independent requests in-flight at once) and is a pretty significant increase in MT/s, DDR5 JEDEC specs are beating top-binned DDR4 kits and DDR5 JEDEC is absolutely slamming the 3200-3866 kits that most people actually buy. Actual DDR5 performance kits will have similar latency to what the current performance DDR4 kits do so that won't be an issue.

It's pretty unrealistic to try to argue that DDR5 at hilarious prices should be compared to bargain-basement DDR4 3200 instead of high-priced 4000+ low-CL models. You can get 4-7% (or more) performance benefit today by splashing out for some DDR4-4400/CL18 RAM vs slower RAM. The minor bandwidth bump by going with DDR5-4800/CL40 or whatever is going to come at the cost of latency.

Which is my entire point: DDR5 at a given price point is unlikely to be significantly faster than DDR4 at a similar price point at launch. Obviously that'll change over time, but anyone hoping that Alder Lake using it will allow it to perform noticeably faster than a similarly-priced DDR4 setup is likely to be disappointed.

movax posted:

The main advantage I see for the faster and faster PCIe specs for consumers is just needing less lanes and therefore less pins to hit target speeds. Lot of stuff (i.e. 10 GbE NICs) eating 2-4 lanes when they could eat 1-2. We don't need x16 4.0 / 5.0 links on the desktop but having smaller slots / more M.2 slots for various devices / more ThunderBolt / etc could be pretty useful. Storage especially -- that stuff is almost always physical lane limited or physical case-size limited, not CPU limited.

You're right, but the moment you start talking about 10Gb NICs you're already way into niche user space--there's not a whole lot of push for it, as can be seen by how tepid the adoption of even 2.5GbE networking has been. I think it's easy for us in this thread to forget that the vast majority of people (even enthusiasts) have a setup that's a single GPU, a SSD, maybe a second SSD for games or whatever, 1Gb networking, and then a mess of USB peripherals. High end NICs, multiple GPUs, multiple PCIe4 SSDs, etc., are all some small fraction of a percent for adoption. Most of the push for more PCIe-anything isn't coming from desktop users.

I'll agree with you that I'd love to see more TB ports--hopefully TB4 being less of a dick about things than TB3 will help push adoption there.

DrDork fucked around with this message at 21:45 on Mar 6, 2021

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

Ika posted:

I know its shared, but a lot of the SKUs have L3 cache scaling with number of cores. Possibly having to do with die area allocation. Another thought: with regression to 14nm cache takes up more die and is easier to cut than CPU logic.

It does scale with core count. For many generations, Intel's L3 architecture is that each core has a local L3 slice. The total size of L3 is the number of cores times the L3 slice size in that processor generation.

Usually. Sometimes they disable part of the L3 slice associated with each core for yield and/or market segmentation. Another exception is in the Xeon space. The die that's taped out always has N cores and N L3 slices, but when they bin out reduced core count versions of a die, they can make special SKUs where cores are disabled but their associated L3 slices are not, raising the L3 cache per core.

Intel uses a hash function to distribute lines across L3 slices. This is intended to automatically distribute the data for every thread across all L3 slices; they don't want hotspots. This is done even though it's lower latency to access the local L3 slice. Intel does this because their L3 cache is intended to provide bandwidth, not just reduced latency. Even for the case of a single active thread, they want to get as many L3 slices involved as possible.

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

DrDork posted:

It's pretty unrealistic to try to argue that DDR5 at hilarious prices should be compared to bargain-basement DDR4 3200 instead of high-priced 4000+ low-CL models. You can get 4-7% (or more) performance benefit today by splashing out for some DDR4-4400/CL18 RAM vs slower RAM. The minor bandwidth bump by going with DDR5-4800/CL40 or whatever is going to come at the cost of latency.

You missed what he said about DDR5 raising the channel count. DDR4 DIMMs are one 64/72-bit channel, DDR5 DIMMs are two 32/40-bit channels. For the same pin count, you get twice as many channels. This matters because as core counts rise, an individual processor chip can generate many more memory requests in parallel; having more independent channels to fulfill them helps with that.

(This is part of why Apple M1 has good memory performance: they used LPDDR4x. Despite sounding like it's just a low power variant of DDR4, LPDDR4 is a rather different protocol, one which already went further down the narrow-channel path than DDR5: it uses 16-bit wide memory channels. M1 has two LPDDR4x chips, each 64 bits wide, giving it a total of eight memory channels.)

There's also a bunch of stuff in DDR5 which is supposed to increase effective bandwidth of the channel (read: fewer dead cycles with no data transfer possible).

BTW, the bandwidth bump won't cost latency, on average. DRAM latency has been roughly constant for a very long time. As DDRn clock speeds go up, that latency "grows" if you're looking at it in terms of cycles, but stays roughly the same if measured in nanoseconds.

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

BobHoward posted:

You missed what he said about DDR5 raising the channel count.
...
BTW, the bandwidth bump won't cost latency, on average. DRAM latency has been roughly constant for a very long time. As DDRn clock speeds go up, that latency "grows" if you're looking at it in terms of cycles, but stays roughly the same if measured in nanoseconds.

I didn't miss it. I'm just looking at it through the lens of what is likely to be actually available at non-insane prices out of the gate. DDR5-4800/CL40 is slated to have noticeably higher latency than all but the worst DDR4, for example. JEDEC says you can get the latency down to only slightly worse than decent DDR4, but it'll still be higher than something like 4000/CL17.

Don't get me wrong--in a year or two once DDR5 has matured a bit and prices have started to come down, it'll crush DDR4 handily. But out of the gate it's not going to be a slam dunk unless you're made of money--and because of that, it's not going to be able to really provide all that much of a benefit to Alder Lake.

NewFatMike
Jun 11, 2015

movax posted:

The main advantage I see for the faster and faster PCIe specs for consumers is just needing less lanes and therefore less pins to hit target speeds. Lot of stuff (i.e. 10 GbE NICs) eating 2-4 lanes when they could eat 1-2. We don't need x16 4.0 / 5.0 links on the desktop but having smaller slots / more M.2 slots for various devices / more ThunderBolt / etc could be pretty useful. Storage especially -- that stuff is almost always physical lane limited or physical case-size limited, not CPU limited.

Yeah, I was just thinking that you could probably run almost any laptop or most desktops off 4 PCIe 5.0 lanes, right? I'm genuinely asking for feedback because it's essentially magic to me.

I don't think we've had a GPU that can fully saturate PCIe 3.0x8 (> PCIe 4.0x4 > PCIe 5.0x2), then one lane for storage and one more for peripherals.

If signal integrity is a given, feels like that might simplify things significantly for mobo makers, right? Or is there a minimum lane count because each lane isn't bidirectional?

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

NewFatMike posted:

Yeah, I was just thinking that you could probably run almost any laptop or most desktops off 4 PCIe 5.0 lanes, right? I'm genuinely asking for feedback because it's essentially magic to me.

I don't think we've had a GPU that can fully saturate PCIe 3.0x8 (> PCIe 4.0x4 > PCIe 5.0x2), then one lane for storage and one more for peripherals.

If signal integrity is a given, feels like that might simplify things significantly for mobo makers, right? Or is there a minimum lane count because each lane isn't bidirectional?

We're now at the cusp of where PCIe 3.0 x8 for a GPU vs x16 is starting to show performance differences. It's slight, but it's there. So PCIe 5 x2 would be the bare minimum, with a lot of people preferring x4 at least--plus who knows what the future will hold, so limiting yourself there would seem like not a great forward-looking plan.

For the rest of it, the question ends up being how many things do you want to throw onto the PCH vs having direct access to the CPU? Bandwidth-wise, though, we've been gettin' on just fine with <8GB/s for the PCH and everything that we hang off of it. So the real question would be how ok are you with having everything other than one SSD (and the GPU) hung off the PCH? If you're fine with it, then sure, a PCIe 5 x1 lane to the PCH and a x2 lane to a SSD gets you about the same bandwidth we've got now.

So 7 lanes minimum, yeah.

But I'd hope they'd take the opportunity to actually push out some new connectivity options, like better support for 10Gb networking, TB4, etc.

Potato Salad
Oct 23, 2014

nobody cares


taqueso posted:

(Model) Number goes up

MaxxBot
Oct 6, 2003

you could have clapped

you should have clapped!!

Perplx posted:

I know not fair but the passive m1 handily beats the new intel space heater at JavaScript benchmarks, also you can’t seem to buy a 7nm anything right now but you can get 5nm iPhone and MacBooks easily.

The lower end Ryzen 5000 SKUs like the 5600X and 5800X have been much more available lately, the 5900X and 5950X are more scarce (although I got a 5900X from the AMD website a month ago). Not to take anything away from how impressive the M1 is.

gradenko_2000
Oct 5, 2010

HELL SERPENT
Lipstick Apathy
going back to the Anandtech article, what is the explanation for the i7-10700K consistently coming out below the i9-9900KS? just the i9 running with better/higher clocks out of the box?

I'm not doubting the conclusions, but I would've wanted to see something like a comparison with all three 8-core parts running at the same set/static clock speed to look at IPC improvements (does that make sense?)

Canna Happy
Jul 11, 2004
The engine, code A855, has a cast iron closed deck block and split crankcase. It uses an 8.1:1 compression ratio with Mahle cast eutectic aluminum alloy pistons, forged connecting rods with cracked caps and threaded-in 9 mm rod bolts, and a cast high

Yeah, the ks part is just running a little faster all core out of the box.

Shrimp or Shrimps
Feb 14, 2012


So, sort of following up to gradenko in a tangential way, and as someone who has absolutely no knowledge about how any of this stuff gets designed or made, how is it that the Intel team can iterate on Comet Lake but achieve somehow worse performance (in gaming)? Like, what's the process for that to happen? How do you try to improve something but end up making it worse (or at the least, not better) despite having worked with similar designs on a similar manufacturing process for however many years it's been?

E: Edited to add "in gaming" as that's what I'm interested in.

Shrimp or Shrimps fucked around with this message at 05:38 on Mar 7, 2021

WhyteRyce
Dec 30, 2001

I'm just going to waive my hands and blame BK and Murthy and to a lesser extent Bob Swan. Yeah...that sounds about right

gradenko_2000
Oct 5, 2010

HELL SERPENT
Lipstick Apathy

Shrimp or Shrimps posted:

So, sort of following up to gradenko in a tangential way, and as someone who has absolutely no knowledge about how any of this stuff gets designed or made, how is it that the Intel team can iterate on Comet Lake but achieve somehow worse performance (in gaming)? Like, what's the process for that to happen? How do you try to improve something but end up making it worse (or at the least, not better) despite having worked with similar designs on a similar manufacturing process for however many years it's been?

E: Edited to add "in gaming" as that's what I'm interested in.

In 2015, Intel released processors based on the "Skylake" architecture. This architecture was based on a 14nm manufacturing process, and the CPUs were marketed as their 6th generation of Core processors (i.e. the i7-6700K)

They followed this up with "Kaby Lake" in 2016. This was an improvement of their 14nm process, and was marketed as their 7th generation of Core processors (i.e. the i7-7700K)

They followed this up with "Coffee Lake" in 2017. This was a further improvement of their 14nm process, and was marketed as their 8th generation of Core processors (i.e. the i7-8700K)

In 2018, Coffee Lake was refreshed as a 9th generation of Core processors, notably in the form of the i9-9900K.

In 2020, Intel released the "Comet Lake" series, yet another improvement of their 14nm process, and was marketed as their 10th generation of Core processors (i.e. the i9-10900K)

All of these processors use the same architecture - as your manufacturing process gets better, your "yields" get better, meaning you can produce more fully functional processors with the same amount of silicon, and fewer of those processors will have flaws. In one respect, this drives down costs, allowing you to sell a quad-core chip (the i3-10100) as a cheap entry-level part that used to be a high-end part (the i7-6700K).

The maturity of the manufacturing process also means that you can clock the chips higher while keeping them stable, and you can squeeze out a little more IPC every time.

However, these are incremental gains, and are never going to match up against a competitor that's iterating on new designs, which can yield larger jumps in performance. Of course, to research and develop a new design takes a lot of time and money, and a bad design might not be much of a gain at all (ex. AMD's Bulldozer architecture).

___

Rocket Lake, this 11th generation that we're talking about with the Anandtech review, is a new design. Or rather, supposedly the design is based on the Tiger Lake archtiecture developed for the 10nm process, but "backported" or adapted for the 14nm process, probably because Intel doesn't have enough 10nm manufacturing capacity just yet to jump directly into producing desktop parts on top of also producing mobile parts. Using a 10nm design but manufacturing it for 14nm parts theoretically allows them to produce new desktop parts without crowding out their existing 10nm commitments.

Unfortunately, as the performance metrics seem to indicate, that kind of compromise might have resulted in a design that's bad enough as we've seen.

Shrimp or Shrimps
Feb 14, 2012


^^ Thanks for the write up, much appreciated! I didn't realize was entirely new and with the backporting stuff. That makes more sense now.

Paul MaudDib
May 3, 2006

TEAM NVIDIA:
FORUM POLICE

Canna Happy posted:

Yeah, the ks part is just running a little faster all core out of the box.

it's actually not even faster in all-core, it's 100 mhz faster only in single-core performance. But it is binned higher so it overclocks higher.

Part of the problem may be the hardware mitigations for smeltdown that were introduced in later steppings of 9th gen (and possibly also in 10th gen as well)...

Eletriarnation
Apr 6, 2005

People don't appreciate the substance of things...
objects in space.


Oven Wrangler

DrDork posted:

You're right, but the moment you start talking about 10Gb NICs you're already way into niche user space--there's not a whole lot of push for it, as can be seen by how tepid the adoption of even 2.5GbE networking has been.

I agree that 2.5GbE networking hasn't really taken off, but I wonder if it's less due to a lack of interest and more a lack of affordable switches. Cost per port on the switch side is not much better than 10G, especially if you want a managed switch which a lot of people who want faster than 1G will.

HalloKitty
Sep 30, 2005

Adjust the bass and let the Alpine blast

Eletriarnation posted:

I agree that 2.5GbE networking hasn't really taken off, but I wonder if it's less due to a lack of interest and more a lack of affordable switches. Cost per port on the switch side is not much better than 10G, especially if you want a managed switch which a lot of people who want faster than 1G will.

It's definitely due to the lack of cheap switches, and also the fact that (afaik) 10 Gbit cards generally don't support it, and will fall back to 1 Gbit; so you need to go out of your way to build a 2.5/5 Gbit network

WhyteRyce
Dec 30, 2001

You can get a 5 port passively cooled 2.5 switch for $100ish now which is way more than a 1G switch but way better than before

I bought it and the first one came with a dead port and the second one required a power cycle after a month of use :(

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

Eletriarnation posted:

I agree that 2.5GbE networking hasn't really taken off, but I wonder if it's less due to a lack of interest and more a lack of affordable switches. Cost per port on the switch side is not much better than 10G, especially if you want a managed switch which a lot of people who want faster than 1G will.

It's a bunch of things combined. The lack of "home affordable" switches has absolutely been a killer--who the hell wants to pay $300 for a 2.5Gb switch when you can get a 1Gb one for $20 or a 10Gb one for...less than $300, frankly, if you're willing to invest in fiber (which at that point you might as well since there's gently caress-all in terms of built-in 2.5Gb NICs except on $400+ motherboards so you're already adding cards in most cases).

That a lot of the faster switches until recently also didn't do meaningful auto-negotiation to slower speeds was both enormously limiting and enormously stupid. Yes, let's design a switch that can do 10GbE, but if you plug a 5GbE card into the other end they negotiate down to 1Gb. Brilliant.

The other issue is just a lack of need. The vast, vast majority of home users simply don't need anything over 1Gb--most people aren't running NASs or mini-data centers. They're streaming Netflix at ~30Mbps through their 100Mbps internet (if they're lucky). Most people would be far more interested in bumping up their internet speed to 100/500/1000Mbps than they are giving a poo poo about their internal network.

Things are starting to get better, but I still don't see it accelerating much for a while. Outside of the datacenter the demand just isn't there, and inside the datacenter the extra power and heat produced by 10GbE vs 10Gb fiber is actually enough of a concern in many cases to rule it out except in edge cases, so the whole "datacenter buys in bulk and the products trickle down to consumers" isn't happening much.

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

In the data center it either doesn’t matter and gigabit is fine or it does and you can do 10 or 25 GbE (or more) for pocket change

Gucci Loafers
May 20, 2006

Ask yourself, do you really want to talk to pair of really nice gaudy shoes?


gradenko_2000 posted:

In 2015, Intel released processors based on the "Skylake" architecture. This architecture was based on a 14nm manufacturing process, and the CPUs were marketed as their 6th generation of Core processors (i.e. the i7-6700K)

:words:

How does Alder Lake fit into the scheme of things?

gradenko_2000
Oct 5, 2010

HELL SERPENT
Lipstick Apathy

Crosby B. Alfred posted:

How does Alder Lake fit into the scheme of things?

Alder Lake is on a new architecture yet again - it's not a Skylake iteration, and it's not Tiger Lake 10nm backported into 14nm.

Alder Lake is going to be based on a 10nm process, and the distinguishing feature is a design that utilizes a combination of "big" cores (high performance) and "little" cores (high efficiency), something that's been tried only previously with ARM designs for mobile devices.

For example, the top-end desktop part is rumored to be eight big cores with hyperthreading, and eight small cores without, so you'll have 16 threads from the big cores and 8 threads from the small cores.

In terms of gaming/desktop performance, the key thing will be whether the big cores are going to be competitive with something like Zen 3+ or Zen 4, since it's unlikely that the little cores are going to be all that useful in applications that don't scale linearly with threads (which are usually productivity apps). There are also rumors that Intel is going to release desktop parts with all-big-cores only, such as eight big cores and no small ones, which would seem to be a cheaper option for someone only chasing after performance.

Only time will tell if this is going to be a marked improvement, since Rocket Lake seems like it's not much of one.

Twerk from Home
Jan 17, 2009

This avatar brought to you by the 'save our dead gay forums' foundation.

PCjr sidecar posted:

In the data center it either doesn’t matter and gigabit is fine or it does and you can do 10 or 25 GbE (or more) for pocket change

From what I understand, 10/40/100gbit is what most older investment is in, but it's not compatible with 25/50/100gbit.

Which sucks for using hand-me-down stuff at home because you really want 25, but most cheap stuff is 10.

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

Twerk from Home posted:

Which sucks for using hand-me-down stuff at home because you really want 25, but most cheap stuff is 10.

Not really sure why you'd bother wanting 25Gb for $$ when you can get 40Gb Infiniband NICs for $50 or less and used switches and cabling for pretty reasonable prices.

It's the same argument of "if you need faster than 10Gb, why would you pay for 25Gb when you can get 40Gb instead?"

Twerk from Home
Jan 17, 2009

This avatar brought to you by the 'save our dead gay forums' foundation.

DrDork posted:

Not really sure why you'd bother wanting 25Gb for $$ when you can get 40Gb Infiniband NICs for $50 or less and used switches and cabling for pretty reasonable prices.

It's the same argument of "if you need faster than 10Gb, why would you pay for 25Gb when you can get 40Gb instead?"

I'm not an IT hardware guy, hence my speculation from the outside, but isn't Infiniband not ethernet?

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

In the datacenter, 25G is one ‘lane’ on a qsfp port on a switch. 40 is four lanes. Even if you actually need ~40G you can double up 2x25 for twice the port density on your ToR. Similar benefits for fiber and optics. It is half a decade old so the older 10/40/100G only gear should be rotating out, and dropping 25G ToR in place of 10G is appealing.

Anyway, yeah; for the home lab the Mellanox gear is great.

Potato Salad
Oct 23, 2014

nobody cares


@twerk yes, and the biggest distinction about infiniband is that it is inherently a remote direct memory access fabric

these days, you can bolt an RDMA protocol atop ethernet if the connection is extremely high quality. RCoE is an example, but it is still not Infiniband©®™

Potato Salad fucked around with this message at 04:19 on Mar 8, 2021

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

Twerk from Home posted:

I'm not an IT hardware guy, hence my speculation from the outside, but isn't Infiniband not ethernet?

There’s been a lot of homelab work on IB; some of the cards and switches can be hacked to hybrid ib/eth mode.

For native IB it’s not something you can plug your synology into but if you want fast linux-linux comms it’s an option.

Potato Salad
Oct 23, 2014

nobody cares


a huge caveat for infinite band at home core driver and hardware compatibility matrices for infiniband are notoriously strict and complex

It is not uncommon for an HPC environment to wait over a year for Intel to publish a certain fix for driver or something that is blocking a major networking or compute upgrade

Gucci Loafers
May 20, 2006

Ask yourself, do you really want to talk to pair of really nice gaudy shoes?


gradenko_2000 posted:

Alder Lake is on a new architecture yet again - it's not a Skylake iteration, and it's not Tiger Lake 10nm backported into 14nm.

Alder Lake is going to be based on a 10nm process, and the distinguishing feature is a design that utilizes a combination of "big" cores (high performance) and "little" cores (high efficiency), something that's been tried only previously with ARM designs for mobile devices.

For example, the top-end desktop part is rumored to be eight big cores with hyperthreading, and eight small cores without, so you'll have 16 threads from the big cores and 8 threads from the small cores.

In terms of gaming/desktop performance, the key thing will be whether the big cores are going to be competitive with something like Zen 3+ or Zen 4, since it's unlikely that the little cores are going to be all that useful in applications that don't scale linearly with threads (which are usually productivity apps). There are also rumors that Intel is going to release desktop parts with all-big-cores only, such as eight big cores and no small ones, which would seem to be a cheaper option for someone only chasing after performance.

Only time will tell if this is going to be a marked improvement, since Rocket Lake seems like it's not much of one.

Seems fair,

I really want to build a new machine and I hope that by the time it's this Fall that it's more than just a paper launch.

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

Potato Salad posted:

a huge caveat for infinite band at home core driver and hardware compatibility matrices for infiniband are notoriously strict and complex

It is not uncommon for an HPC environment to wait over a year for Intel to publish a certain fix for driver or something that is blocking a major networking or compute upgrade

Yes, it adds quite a lot of suffering to your homelab, but most of the reason people have home labs is a desire for suffering.

To bring it back around to the thread topic, Intel bought and promoted their own IB implementation over half a decade ago and then killed it a year or two ago in favor of Ethernet. Shortly thereafter, NVIDIA bought Mellanox, lol.

shrike82
Jun 11, 2005

lol I’m curious what you guys are doing are home that needs that much bandwidth

necrobobsledder
Mar 21, 2005
Lay down your soul to the gods rock 'n roll
Nap Ghost

shrike82 posted:

lol I’m curious what you guys are doing are home that needs that much bandwidth
Decently low latency home NAS / SANs are the primary reason really where iSCSI over Gigabit is super painful to do random I/O off of and 10 GbE and higher greatly improves latency. Infiniband is kinda meant for storage fabric networks really. Also, I'm a madman and like to run Kafka clusters feeding jobs crunching through my video collection at ludicrous speeds and look for bottlenecks for fun. After all, HPC is turning CPU-bound problems into I/O bound problems. I'm totally fun at parties, I swear.

Meanwhile I'm trying to figure out if I should blow the money for a separate Infiniband switch or just settle for 10 GbE forever and stick with just Ubiquiti gear. Currently just doing machine-to-machine 10 GbE and can't really scale out without a switch, period.

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in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

AFAIK , the most popular option is connecting your bad virtualization server to your bad storage server so you can run your bad hobby vms instead of paying do or aws $5/mo and getting a skill that employers actually want to see on your resume.

If you’re deeply committed to poor choices there’s some minikube or k3s in there.

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