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Luigi Thirty
Apr 30, 2006

Emergency confection port.

update:

https://twitter.com/LuigiThirty/status/1066617653807194112

now if I could figure out how to read the onboard flash (for a character ROM) and the onboard memory (for a tilemap region) I’d be set

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eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?
the onboard flash may not be usable in quite that way; it may be just for the FPGA configuration bitstream

the easiest way to deal with the onboard RAM probably won’t be to write your own Verilog for it, but to figure out how to use the FPGA tools to instantiate an “IP block” to interface to it, and then talk to that

that’s also probably the best way to implement something like a UART (or I2C or SPI, or even things like a TDMS interface for DVI or HDMI) since FPGAs often have a bunch of onboard peripheral blocks and/or pre-fab—and pre-validated, and pre-optimized—designs that can be used as-is

this is also a reason I prefer VHDL to Verilog: Verilog feels very much like pre-prototypes “stack layout? just wing it!” C to me whereas VHDL doesn’t just allow but requires a formal separation of interface from implementation; slightly less conducive to hacking, but better for maintainability over the long term as well as modularity

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

eschaton posted:

this is also a reason I prefer VHDL to Verilog: Verilog feels very much like pre-prototypes “stack layout? just wing it!” C to me whereas VHDL doesn’t just allow but requires a formal separation of interface from implementation; slightly less conducive to hacking, but better for maintainability over the long term as well as modularity

i started out my career writing vhdl, and found myself much more productive after switching jobs to an employer that was a verilog shop. vhdl is certainly a cleaner base design, but requires you to write a ton of boilerplate and typecasts to get anything done, and i don't remember getting anything actually useful out of the extra formalism which i miss in verilog

also modern verilog is systemverilog, and it's generally caught up to and even surpassed vhdl. i don't think modern vhdl has anything comparable to interfaces, for example. or SV assertions. (there's an assert construct in vhdl but SVA has these really slick 'temporal operators' which let you test things like "if A in this cycle, B must be true in the next".) there's also the OOP features, not used for synthesizable RTL but very important to the UVM verification framework, which i'm not aware of an equivalent for in vhdl

feels like all the industry momentum is behind SV at this point, it's an actively updated standard and vhdl hasn't seen anything since 2008

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull
oh and luigi, have you tried writing a behavioral model of the RAM you want? idk how good the tools for lattice fpgas are these days, but for xilinx i can just write something like this to create a memory and the tools will automatically convert it to one or more xilinx block RAMs for me (parameterized size-flexible version left as an exercise for the reader):

code:
module my_ram (
    input logic clk,

    input logic [9:0] raddr,
    output logic [7:0] rdata,
    input logic ren,

    input logic [9:0] waddr,
    input logic [7:0] wdata,
    input logic wen
);

logic [1023:0] [7:0] ram;

always_ff @(posedge clk) begin
    if (ren) rdata <= ram[raddr];
    if (wen) ram[waddr] <= wdata;
end

endmodule

r u ready to WALK
Sep 29, 2001

This is the most delightful thing and I really want to do this for my SE/30



https://68kmla.org/forums/index.php?/topic/54476-wifi-extension-development-thread/&

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

r u ready to WALK posted:

This is the most delightful thing and I really want to do this for my SE/30



https://68kmla.org/forums/index.php?/topic/54476-wifi-extension-development-thread/&

NICE!!

Jonny 290
May 5, 2005



[ASK] me about OS/2 Warp
https://imgur.com/a/TvJ8FGK

huge rear end antenna mount went on the expedition today

Nomnom Cookie
Aug 30, 2009



Jonny 290 posted:

https://imgur.com/a/TvJ8FGK

huge rear end antenna mount went on the expedition today

sw8

Stack Machine
Mar 6, 2016

I can see through time!
Fun Shoe
Can confirm the Lattice tools will infer block RAM from arrays. The writes have to be synchronous to a clock edge. BobHoward's code looks something like what I've used, but the array itself in my code was of type "reg". That may or may not matter. Logic synthesis is still in the stone age.

EIDE Van Hagar
Dec 8, 2000

Beep Boop

Jonny 290 posted:

https://imgur.com/a/TvJ8FGK

huge rear end antenna mount went on the expedition today

luv2holesaw

Jonny 290
May 5, 2005



[ASK] me about OS/2 Warp

step bit actually. i bought a cheap HF drill because crackheads porchsniped my old drill, and it started smoking on the third 1/4" hole. so i returned that trash and bought a 6.6 amp metal case drill with a 2:1 gear reduction. wont go over 1000 rpm but its perfect for hole saws and step bits and high torque stuff

r u ready to WALK
Sep 29, 2001

help i can't stop buying obsolete computers



It was just $40 for two G4 towers and the display, i shall treasure them always



It is neat because it was the last CRT apple sold, but also amazingly bad because it steals around 100 watts of power through the ADC connector and can't really be used with anything other than the G4 MDD towers with the beefy loud PSUs.

haveblue
Aug 15, 2005



Toilet Rascal
I wish people had started calling those speed holes G4s

Endless Mike
Aug 13, 2003



sorry about your bad purchasing decisions op

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

Stack Machine posted:

Can confirm the Lattice tools will infer block RAM from arrays. The writes have to be synchronous to a clock edge. BobHoward's code looks something like what I've used, but the array itself in my code was of type "reg". That may or may not matter. Logic synthesis is still in the stone age.

“logic” is a new type in systemverilog designed to replace reg and wire with one type. logic is p much “reg, but can also be used as if it was a wire, and we made it illegal to use it as a reg and a wire at the same time so that compilers and linters can save you from footbullet, also the reserved keyword you use to declare nearly every variable no longer suggests theyre all registers”.

if lattice tools supported SV, reg/logic would be equivalent. sadly i just checked and it seems that lattice synthesis is stuck in the dark ages. unless you’re able to use the third party toolchain synplify pro ($$$), you’re stuck with probably verilog 2001, so reg it is

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

BobHoward posted:

also modern verilog is systemverilog, and it's generally caught up to and even surpassed vhdl. i don't think modern vhdl has anything comparable to interfaces, for example. or SV assertions. (there's an assert construct in vhdl but SVA has these really slick 'temporal operators' which let you test things like "if A in this cycle, B must be true in the next".) there's also the OOP features, not used for synthesizable RTL but very important to the UVM verification framework, which i'm not aware of an equivalent for in vhdl

sounds like I need to learn SystemVerilog then

also reminder that Clash is a thing and is interesting

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

r u ready to WALK posted:

help i can't stop buying obsolete computers



It was just $40 for two G4 towers and the display, i shall treasure them always



It is neat because it was the last CRT apple sold, but also amazingly bad because it steals around 100 watts of power through the ADC connector and can't really be used with anything other than the G4 MDD towers with the beefy loud PSUs.

nice! those PSUs are also fragile so they need refurbishing eventually

a 120GB SATA SSD will work great in those systems via a cheap ATA-SATA bridge and they will feel lightning fast running Mac OS 9

you are running the “Mac OS 9 Lives” distribution of Mac OS 9 right?

EIDE Van Hagar
Dec 8, 2000

Beep Boop

eschaton posted:

sounds like I need to learn SystemVerilog then

also reminder that Clash is a thing and is interesting

yeah if you want to do any of it professionally it is all systemverilog and the testbenches are also all oop (ovm/uvm) now.

Luigi Thirty
Apr 30, 2006

Emergency confection port.

the RAM is all block ram hooray

I set up data and address busses between RAM, my LEDs, and the CPU module

I rigged it up to read a byte from RAM and write it to the display and it worked :3:

now I just need to start writing a RISC-V processor module and I’ll be somewhere around 1977

r u ready to WALK
Sep 29, 2001

eschaton posted:

you are running the “Mac OS 9 Lives” distribution of Mac OS 9 right?

of course
it was the only one i could get to boot my fastest g4

unfortunately it seems like the 533mhz "digital audio" g4 i got from this guy is just barely too new to run macos 8.6 for maximum after dark module compatibility :(

apple removed support for compressed resources in 9.x for some reason and it breaks a bunch of old software

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

Luigi Thirty posted:

now I just need to start writing a RISC-V processor module and I’ll be somewhere around 1977 1987

just like the first SPARC!

Luigi Thirty
Apr 30, 2006

Emergency confection port.

eschaton posted:

just like the first SPARC!

i only have a one-bit video display so i'm thinking more PET than SPARCStation

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

Luigi Thirty posted:

i only have a one-bit video display so i'm thinking more PET than SPARCStation

most Suns (and other workstations) before the 1990s also typically had one-bit video

of course right now you’re doing beam racing composite rather than a high speed raster…

Luigi Thirty
Apr 30, 2006

Emergency confection port.

my oscillator is 16MHz, my pixel clock is 8MHz, and I don't have a lot of RAM to spare so I have a tilemapped console. if I hooked up a physical SRAM chip I could fit an entire framebuffer into memory... but I don't have any I/O pins left on the babby board

i could probably add hardware sprites too if i wanted

Raluek
Nov 3, 2006

WUT.

r u ready to WALK posted:

help i can't stop buying obsolete computers



It was just $40 for two G4 towers and the display, i shall treasure them always



It is neat because it was the last CRT apple sold, but also amazingly bad because it steals around 100 watts of power through the ADC connector and can't really be used with anything other than the G4 MDD towers with the beefy loud PSUs.

i kinda hate you. ive been keeping an eye out for one of those displays for awhile now, but $80 at the flea aint gonna cut it. is it a dual 1.42?

eschaton posted:

nice! those PSUs are also fragile so they need refurbishing eventually

a 120GB SATA SSD will work great in those systems via a cheap ATA-SATA bridge and they will feel lightning fast running Mac OS 9

you are running the “Mac OS 9 Lives” distribution of Mac OS 9 right?

or a bigger drive, if you want to dual boot. they arent limited to 120 like the earlier G4s

if you want to boot a generic os9 install (rather than the one for unsupported G4s) its a single OF line to enable os9 booting on a fw800

You Am I
May 20, 2001

Me @ your poasting

Got the UltraSatan for my Atari ST in the mail last night. Not sure if I have the time this coming weekend to set it up on the STE, but will be cool to see how it runs. It came with a SD card set up all ready for use, no need to do any crazy partitioning or set ups.

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

Luigi Thirty posted:

my oscillator is 16MHz, my pixel clock is 8MHz

are you using the pll? it can synthesize a wide range of frequencies from the 16 MHz oscillator input if you need more options

nice project btw!

Luigi Thirty
Apr 30, 2006

Emergency confection port.

You Am I posted:

Got the UltraSatan for my Atari ST in the mail last night. Not sure if I have the time this coming weekend to set it up on the STE, but will be cool to see how it runs. It came with a SD card set up all ready for use, no need to do any crazy partitioning or set ups.

you just need a driver that runs in your AUTO folder iirc

Luigi Thirty
Apr 30, 2006

Emergency confection port.

BobHoward posted:

are you using the pll? it can synthesize a wide range of frequencies from the 16 MHz oscillator input if you need more options

nice project btw!

I just have a clock divider. I’m not using icecube (i downloaded it but it claims my license is invalid lol) so idk how to use the PLL primitive with ice-whatever apio uses

the tilemap engine operates at 16MHz so it can update the pixel out register faster than the dot clock which is 8MHz

the CPU (which currently is just an instruction fetcher and decoder) operates off the 16MHz input (idk how real CPUs do this but it made sense to me) with each pipeline step taking two 16MHz cycles

Luigi Thirty fucked around with this message at 11:08 on Nov 27, 2018

the wizards beard
Apr 15, 2007
Reppin

4 LIFE 4 REAL
can anyone recommend some verilog resources? I learnt it in back in school and am considering a career move. so far I have read some language specs and done about a hundred problem on hdlbits, looking at doing some small commits to some open source projects. I don't know any systemverilog and probably don't really understand all the verilog2001 features

e: familiar with nandland, zipcpu, asic-world already. worked through this list as well: http://fpgacpu.ca/fpga/hdl/index.html

the wizards beard fucked around with this message at 15:59 on Nov 27, 2018

Jonny 290
May 5, 2005



[ASK] me about OS/2 Warp
the ford antenna situation is rapidly escalating

EIDE Van Hagar
Dec 8, 2000

Beep Boop
get some guy wires up there attached to the bumpers and then I'll be impressed :colbert:

Jonny 290
May 5, 2005



[ASK] me about OS/2 Warp
i actually picked up a length of 1x2 furniture grade oak that i'm going to bolt to the roof rail and then kick over for a rigid support

EIDE Van Hagar
Dec 8, 2000

Beep Boop

the wizards beard posted:

can anyone recommend some verilog resources? I learnt it in back in school and am considering a career move. so far I have read some language specs and done about a hundred problem on hdlbits, looking at doing some small commits to some open source projects. I don't know any systemverilog and probably don't really understand all the verilog2001 features

e: familiar with nandland, zipcpu, asic-world already. worked through this list as well: http://fpgacpu.ca/fpga/hdl/index.html

there are some good resources out there on eda playground if you want to learn any of the systemverilog verification features. here's a basic uvm testbench hooked up to a simole dut that I made if you ever want to do uvm verification stuff.

https://www.edaplayground.com/x/2GYV

that uses some of the oop features of systemverilog.

if you are doing synthesizable rtl then the resources you posted are pretty good, i mostly do verification so i might not be the best to ask about that tho.

r u ready to WALK
Sep 29, 2001

The RGB to SCART cable for my ST arrived today so I could finally test it, it refused to boot and had really glitched video but after reseating / jiggling the socketed chips it sprung to life and it looks to generally be in good condition





Norwegian TOS :haw:

I don't have the floppy drive for it and I'm a total Atari incompetent, will the Ultrasatan work with just the TOS ROM or does it have to boot from a floppy, I see people mention that it needs a driver...

You Am I
May 20, 2001

Me @ your poasting

Holy poo poo an OG ST, like external PSU and FDD model. And far far better 9 pin port location compared to its later models.

I think you'll need either an external FDD or a Gotek setup in an external casing for your model. Also worth updating the TOS to 1.04.

Luigi Thirty posted:

you just need a driver that runs in your AUTO folder iirc
Yeah, the seller had linked the resources in his eBay description.

Luigi Thirty
Apr 30, 2006

Emergency confection port.

r u ready to WALK posted:

The RGB to SCART cable for my ST arrived today so I could finally test it, it refused to boot and had really glitched video but after reseating / jiggling the socketed chips it sprung to life and it looks to generally be in good condition





Norwegian TOS :haw:

I don't have the floppy drive for it and I'm a total Atari incompetent, will the Ultrasatan work with just the TOS ROM or does it have to boot from a floppy, I see people mention that it needs a driver...

the ultrasatan plugs into the Atari’s SCSI port. if the SD card contains the driver it’ll boot from it automatically. Newer TOSes work better and have faster and more reliable disk access

otherwise you can use a boot disk with the driver on it like any other computer

Luigi Thirty
Apr 30, 2006

Emergency confection port.

I... guess my RISC pipeline being a big chain of if opcode == x then... statements is right but

I mean it works so far

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

the wizards beard posted:

can anyone recommend some verilog resources? I learnt it in back in school and am considering a career move. so far I have read some language specs and done about a hundred problem on hdlbits, looking at doing some small commits to some open source projects. I don't know any systemverilog and probably don't really understand all the verilog2001 features

e: familiar with nandland, zipcpu, asic-world already. worked through this list as well: http://fpgacpu.ca/fpga/hdl/index.html

did you skim through sunburst design's papers page while working through that? a lot of it's out of date, because he wants to sell you training courses using his modern material and these are just papers he's given at industry conferences, but there's some good stuff in there

also i recommend downloading the language reference manual from ieee since (unlike some ieee standards) it's available free of charge:

https://ieeexplore.ieee.org/document/8299595

the LRM probably isn't a great way to learn the language but it's good to have a reference

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BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

r u ready to WALK posted:

The RGB to SCART cable for my ST arrived today so I could finally test it, it refused to boot and had really glitched video but after reseating / jiggling the socketed chips it sprung to life and it looks to generally be in good condition

that brings back memories of the standard advice for someone with a broken ST: "pick it up a couple inches off the table, drop flat to reseat the chips"

which i do not recommend especially now that they are antiques, but possibly sometimes actually worked

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