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Kazinsal posted:I've never met the guy but DEC folks who worked with him said he thought the entire I/O and userspace processes/daemons model of Unix was obsolete before it even left Bell Labs and it held back small-scale computing for years, and a book that interviewed some folks who worked on NT with him described him as considering Unix system design as his Moriarty a la Sherlock Holmes as well as considering it "a junk operating system designed by a committee of PhDs". steve ballmer pretty much got him on board by telling him it was a chance to write a microcomputer OS that scaled up to servers and minicomputing that would displace Unix. he doesn't do interviews really so it's hard to get first-hand accounts from the man plz tell me more about VAX i/o vs unix because i know nothing about either
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Feb 3, 2022 14:24
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Sweevo posted:plz tell me more about VAX i/o vs unix because i know nothing about either Classic unix model - call the read() syscall to get some data from a file handle. Blocks until that data has arrived, your (back in the day) single threaded process is sitting there doing absolutely nothing until it does. Or until you get an error. Like the dreaded EINTR which means 'you got a signal, no i'm not going to just restart the system call so ask me again'. VMS model - call read(), give it a callback, VMS will call your callback when your data arrives. In the meantime you can go about your day, do calculations, even kick off a bunch more I/O operations, and the kernel will do its best to schedule them for maximum efficiency, quite possibly in parallel (consider if you're reading from two different physical discs for eg). The latter is a bit more complicated to implement and to work with but more efficient. Importantly, though you can turn it into the former system by doing your read() and then just waiting for the callback anyway, but you can't do the reverse.
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Feb 3, 2022 14:52
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hi im just makin an anti-VAX joke ok bye
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Feb 3, 2022 17:35
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feedmegin posted:'you got a signal, no i'm not going to just restart the system call so ask me again'. pc luser lol
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Feb 11, 2022 00:53
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someone talk me out of buying a vax https://www.ebay.ca/itm/304204811759
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Feb 11, 2022 04:27
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how much is the shipping?
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Feb 11, 2022 04:32
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don't buy a vax
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Feb 11, 2022 04:33
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hundred bucks since I'm in canada 
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Feb 11, 2022 04:33
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no drives or tapes and you'll need a vt if you don't already have one. i wouldn't unless you're trying to bootstrap a collection here
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Feb 11, 2022 05:02
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Good luck trying to find some software to run on it. What's are you gonna find a bunch of 30-year old floppies that still work?
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Feb 11, 2022 06:29
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Poopernickel posted:30-year old floppies that still work there's a lot of these in yospos
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Feb 11, 2022 06:37
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the hard drive being missing is a pain because i've heard VAXes are pretty picky about what drives work. the boot drive must be 1.05GB or less for example
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Feb 11, 2022 13:36
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There's a raspberry pi scsi emulation project that apparently has been made to work with VAX boxes: https://youtu.be/dMgAJnxiYGQ
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Feb 11, 2022 18:09
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Sweevo posted:the hard drive being missing is a pain because i've heard VAXes are pretty picky about what drives work. the boot drive must be 1.05GB or less for example not a big deal since the SCSI2SD, you can set the size and identifier to match what the DEC bootstraps expect and it’ll just work RZ26 works for a ton of stuff
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Feb 15, 2022 10:49
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scsi2sd will be here next week, AUI transceiver the week after, and the VAX and console cable should be here the week after that dear ebay seller: sned the yosvax
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Feb 15, 2022 10:51
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Kazinsal posted:scsi2sd will be here next week, AUI transceiver the week after, and the VAX and console cable should be here the week after that i gotta say i respect this commitment to silly irrelevant old computer platforms because the same brain disease is why i have my pismo powerbook running mac os 9
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Feb 15, 2022 19:39
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EIDE Van Hagar posted:i gotta say i respect this commitment to silly irrelevant old computer platforms because the same brain disease is why i have my pismo powerbook running mac os 9  also an ibook with 8.6. and a mac classic with system 7.5
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Feb 15, 2022 20:41
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Kazinsal, are you going to set up VMS on SIMH initially and then transfer the disk images to an SD card to boot on the VAX? if so be aware that SIMH will spend an extra block or two to the image with its own metadata rather than put that in a separate file, but it’s easy to deal with since it’s just an append this way you can get VMS 7.3 set up with all the layered products etc. and maybe even get MONSTER-Helsinki set up if you want to run the YOSMUD
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Feb 15, 2022 22:29
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(I can provide the simple tweak needed to build MONSTER-Helsinki 1.0.6 with the final VAX Pascal compiler)
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Feb 15, 2022 22:30
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eschaton posted:Kazinsal, are you going to set up VMS on SIMH initially and then transfer the disk images to an SD card to boot on the VAX? yeah, that's basically the plan, that or set the SCSI2SD up to present two devices; one hard disk, one CD drive containing the VMS image. eventually I'd like to have multiple hard disks on one card so I can boot into different OSes and so I can fiddle with my own low-level VAX code
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Feb 15, 2022 22:37
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SYSV Fanfic posted:Just want to add that this check is the default behavior. You can disable these checks x86_64, and AArch64 and and Linux (probably windows too) uses the highest bits to tag memory regions. The tag bits extend from left to right, when the architecture grows the canonical area, it grows from right to left. It's going to be awhile before there is a risk of them overlapping. Where does Linux do this on AMD64?
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Feb 16, 2022 03:36
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you definitely cannot disable canonical address checking in x86-64. it always raises a general protection fault (or a stack fault if it's a stack reference). you *could* intentionally dereference non-canonical addresses anyways and then trap on that in your #GP handler but the context switching/interrupt latency cost would suck so you'd want to use it extremely sparingly and also as soon as AMD or Intel decides to implement PML6 you can't do that anymore because the whole 64-bit virtual address space will be available Kazinsal fucked around with this message at 04:04 on Feb 16, 2022 |
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Feb 16, 2022 04:01
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that's what I thought
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Feb 16, 2022 04:15
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how about some HP hardware? my HP rp2430 now believes it’s an rp2470 and will boot MPE/iX 7.5
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Mar 2, 2022 13:17
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hell yes get that HP hardware in here! what's the difference between the rp2430 and rp2470 and what did you have to do to make the former think it's the latter? does MPE/iX normally not boot on the 2430?
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Mar 2, 2022 18:07
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MPE/iX normally doesn’t boot on a system that’s not specifically enabled for it by a few values in EEPROM (“stable storage” in HP terms) which let HP sell the same hardware badged as HP 3000 for two to five times what they charged for it badged as HP 9000 and running HP-UX I had to interrupt the boot process, which then let me access a secret tool in the Service menu off the main boot menu, and run that to change my hardware model and part number, some model strings that are checked at boot, and the bit that says whether MPE is allowed to run here’s an example of how the process works
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Mar 2, 2022 22:26
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oh and the main reason to tell my rp2430 it’s an rp2470 is because, while the systems used the same main logic board and ROM, the rp2430 is a single-CPU system with a 2GB RAM ceiling and three PCI slots while the rp2470 supports one or two CPUs, all five PCI slots, and up to 8GB of RAM—it’s just held back by the model string
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Mar 2, 2022 23:01
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whoa neat
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Mar 3, 2022 04:27
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i own a vaxstation and an alphaserver. my network is set up for netbooting VMS and decnet
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Mar 3, 2022 04:37
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eschaton posted:MPE/iX normally doesn’t boot on a system that’s not specifically enabled for it by a few values in EEPROM (“stable storage” in HP terms) which let HP sell the same hardware badged as HP 3000 for two to five times what they charged for it badged as HP 9000 and running HP-UX that's friggin cool! vax update: still in ebay purgatory (also known as erlanger, kentucky) 
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Mar 3, 2022 04:57
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Thanks for the explanation of the evolution of the x86 memory model. It really explains all those compile switches in early Linux kernels. ACPI seems like a real shitshow. I've done embedded powerpc development so I always wondered if the i/o address space for x86 is still in use, since it seemed so clunky. I'm sorta happy that it was just an ISA thing. I was part of a student run lab that had a DEC Alpha desktop that had a high fsb speed but didn't seem to be noticably faster than the celeron 300a desktops that the rest of us had for personal use. Probably because we just ran Linux on it and maybe browsed the web on it occasionally. And, of course, the audio didn't work, so it still never got used that much.
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Mar 3, 2022 08:17
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sb hermit posted:I was part of a student run lab that had a DEC Alpha desktop that had a high fsb speed but didn't seem to be noticably faster than the celeron 300a desktops that the rest of us had for personal use. Probably because we just ran Linux on it and maybe browsed the web on it occasionally. And, of course, the audio didn't work, so it still never got used that much. our student lab had a surplus of vt220s and zero concern for power consumption, so fun things like vtclock came to exist:  you might think "wow, a vt220 clock must suck down the juice", but that's nothing compared to a vt220 clock that's being driven by a 4u alpha axp another energy-hungry appliance was the lab jukebox -- this vt220 displayed an ncurses mp3 player running on an old hp apollo workstation (mmmm pa-risc) running debian. amazingly sound worked in linux twenty years go on it -- unless you tried to ssh in while an mp3 was playing; then you got a nice stutter. edit: come to think of it, we didn't really care about power consumption at home either. for a minute we had a vtclock in our living room, powered by (I think) a housemate's vax, hiding behind the couch. outhole surfer fucked around with this message at 08:41 on Mar 3, 2022 |
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Mar 3, 2022 08:35
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I passed on getting the haul of free VAX stuff. It would have been fun to play with it all but the guy was being shady about exactly what was included. Eventually he let slip that he'd already had people come and pick through the pile, so I figure all the good stuff was gone and he wanted me to drive 90 minutes each way for a van full of 10mb coax ethernet crap and broken printers.
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Mar 3, 2022 13:23
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So how does (or I guess “did”) Itanium stack up against x86-64? In another timeline could have been successful or was it always probably going to be a technological dead end?
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Mar 4, 2022 01:50
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it required way way too much from compilers to actually exploit well for random software written in C business software written in COBOL may have fared better, I know FORTRAN code did; my rx2660 with DEC FORTRAN running some numeric benchmarks did really impressively for the era in which it was made, on par with some much newer x86-64 hardware people were also able to make databases fly and the HP 3000 people were legit pissed that after promoting it to select customers, HP shelved the work they were doing to port MPE/iX to Itanium (along with shelving the entire HP 3000)
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Mar 4, 2022 09:48
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Itanium would have been a phenomenal architecture if compilers were as magic as the Itanium design team thought they were, but for the general purpose you just can't magically optimize everything for VLIW (very long instruction word) architectures -- the most successful VLIW architecture I can think of is ATI/AMD TeraScale, which is the underlying architecture for the Radeon HD 2000 through 6000 series GPUs the Itanium architecture also had some absolutely insane, end-developer-hostile stuff like having 128 general-purpose registers + 128 float registers, with register windowing, exposing branch prediction registers to the programmer, and 128 "special purpose" registers for doing stuff like telling the hardware how to spill rotated register window contents onto a stack if needed because the instruction set lets you rotate the register windows in blocks of 32 for hyper-parallelism intel straight up designed it with the idea that the compiler would just batch together up to six different instructions into a single giant instruction word "bundle" and throw in branch prediction hints in the mix. in practice this meant that you could slam a shitload of fused multiply-adds into a single execution cycle. in practice, everything else sucked and five years into Itanium's life, GPGPU started to show up and now you could do hundreds of FMA instructions per cycle on a $500 consumer PCIe card that had its own ultra-fast slab of memory e: the idea of Explicitly Parallel Instruction Computing is cool but it's totally garbage for the average use case and great for highly regular parallelizable operations, which is why modern CPUs just have a whole bunch of mostly independent CPU cores with their own ALUs/branch predictors/etc. and any highly parallel numerical work gets offloaded to GPUs Kazinsal fucked around with this message at 10:17 on Mar 4, 2022 |
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Mar 4, 2022 10:12
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as far as the isa goes, itanium is really weird first, it’s got a poo poo-ton of registers, both integer and floating-point. there are 32 static registers, meant as scratch between calls, and then a window of 96 more registers that you can rotate during calls to save data without spilling to the stack (at least, not directly in the compiler; if you have enough calls to overflow the register window, it still has to spill, of course). that’s almost an unreasonable number of registers. and that’s for each of integer and fp, and then there are a bunch of specialized registers for things like conditions. it’s really a lot the bigger thing is that itanium wants to run instructions in parallel by default. instructions are 41 bits, and there are three packed into a 128-bit instruction bundle. instructions within a bundle always run in parallel, so if you have dependencies, like if one instruction adds an offset to a pointer and then another loads from that pointer, they need to go in separate bundles. but they can’t just go in separate bundles: you need the second bundle to say specifically that it has a dependency on a previous bundle and so cannot be run in parallel so it turns out that superscalar architectures are pretty good at running things in parallel already. the itanium approach is better in some ways: superscalar architectures can definitely suffer from false dependencies, especially with memory, and itanium can communicate that the processor doesn’t have to worry about that. but to do that, the compiler also has to know that there isn’t a dependency. for simple data dependencies in registers, this is straightforward. for memory, it usually means doing an alias analysis. this is a lot easier in fortran, which has very limited pointers and very strong default assumptions about aliasing, than it is in (say) c but also the compiler has to reorder a lot of stuff just to try to fill bundles so that you don’t end up with appallingly bad code density. the problem is that superscalar architectures get most of the potential value here without all the extra pain. and probably itanium would still have benefitted from using standard superscalar techniques to recognize potential for parallelism even when the instruction stream said there might be a dependency; i don’t know how much of that they did anyway, below the isa level, itanium was positioned as a server / hpc architecture, so its chipsets were designed for beefy systems. in particular, they had a lot of memory bandwidth. so yeah, databases usually aren’t computation-bound, but they can absolutely be memory-bound depending on the workload, and itanium machines were good at that. and they could also be very good at certain hpc workloads that did a million things in parallel over big datasets
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Mar 4, 2022 11:02
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I thought IBM's Cell architecture was ambitious but crazy. Itanium just takes the cake. Having a language like Fortran where the intricacies of the ISA would be abstracted is definitely a plus, but probably still quite limited. Maybe even using a data oriented language like Prolog or a new language altogether would be better. It's funny how the promise of "compilers will make everything magically parallelizable and will magically max out all cores" has continued to come up empty. Unless you want to use go or something. And even now, Intel's latest x86 chips are now using heterogenous compute cores where not all cores are beefy cores for doing anything. Some cores are more power efficient. It's a good step.
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Mar 4, 2022 11:34
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Speaking of x86 memory management, does anyone know if Intel is going to try to revive some aspect of its ill fated dma engine? https://en.m.wikipedia.org/wiki/I/O_Acceleration_Technology It just seems cool to have an entire chip, separate from the CPU, to just seize dma channels to move data or zero out regions. Maybe it would be better suited for NUMA architectures or maybe it's just a terrible idea altogether.
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Mar 4, 2022 11:40
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Thanks for the responses! Exposing the branch prediction registers to the programmer sounds absolutely insane. There’s giving people enough rope to hang themselves, and then there is passing out nooses when people are just trying to mind their own business.
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Mar 4, 2022 15:57
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